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ds1873 ________________________________________________________________ maxim integrated products 1 19-4986; rev 1; 11/09 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. evaluation kit available sfp+ controller with analog ldd interface general description the ds1873 controls and monitors all functions for sff, sfp, and sfp+ modules including all sff-8472 func- tionality. the ds1873 provides apc loop, modulation current control, and eye safety functionality. the ds1873 continuously monitors for high output current, high bias current, and low and high transmit power to ensure that laser shutdown for eye safety requirements are met without adding external components. six adc channels monitor v cc , temperature, and four external monitor inputs (mon1?on4) that can be used to meet all monitoring requirements. mon3 is dif- ferential with support for common mode to v cc . two digital-to-analog (dac) outputs with temperature- indexed lookup tables (luts) are available for addition- al monitoring and control functionality. applications sff, sfp, and sfp+ transceiver modules features ? meets all sff-8472 control and monitoring requirements ? six analog monitor channels: temperature, v cc , mon1?on4 mon1?on4 support internal and external calibration scalable dynamic range internal direct-to-digital temperature sensor alarm and warning flags for all monitored channels ? four 10-bit delta-sigma outputs with 36 entry temperature luts laser bias controlled by apc loop and temperature lut to compensate for tracking error laser modulation controlled by 72-entry temperature lut two additional dacs controlled by one 72-entry and one 36-entry temperature lut ? digital i/o pins: five inputs, five outputs ? comprehensive fault-measurement system with maskable laser shutdown capability ? flexible, two-level password scheme provides three levels of security ? 120 bytes of password-1 protected memory ? 128 bytes of password-2 protected memory in main device address ? 256 additional bytes located at a0h slave address ? i 2 c-compatible interface ? +2.85v to +3.9v operating voltage range ? -40? to +95? operating temperature range ? 28-pin tqfn (5mm x 5mm) package thin qfn (5mm 5mm 0.8mm) top view 26 27 25 24 10 9 11 scl txf los in1 txd 12 rselout bias gnd mon2 gnd v cc n.c. 12 dac2 4567 2021 19 17 16 15 v cc losout mon3p mon4 txdout rsel sda mod 3 18 28 8 out1 gnd dac1 23 13 mon3n n.c. 22 14 mon1 refin ds1873 *ep + *exposed pad. pin configuration ordering information + denotes a lead(pb)-free/rohs-compliant package. t&r = tape and reel. * ep = exposed pad. part temp range pin-package ds1873t+ -40c to +95c 28 tqfn-ep* ds1873t+t&r -40c to +95c 28 tqfn-ep*
ds1873 2 _______________________________________________________________________________________ absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 mod, bias, dac1, dac2 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 analog quick trip characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 analog voltage monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 digital thermometer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 ac electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 timing characteristics (control loop and quick trip) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 i 2 c ac electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 nonvolatile memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 typical operating circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 detailed description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 bias dac/apc control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 bias and mod output control during power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 bias and mod dacs as a function of transmit disable (txd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 apc and quick-trip timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 monitors and fault detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 monitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 five quick-trip monitors and alarms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 six adc monitors and alarms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 adc timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 right-shifting adc result . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 differential mon3 input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 enhanced rssi monitoring (dual-range functionality) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 low-voltage operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 power-on analog (poa) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 delta-sigma outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 digital i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 los, losout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 in1, rsel, out1, rselout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 txf, txd, txdout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 transmit fault (txf) output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 die identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 table of contents sfp+ controller with analog ldd interface
ds1873 _______________________________________________________________________________________ 3 i 2 c communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 i 2 c definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 i 2 c protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 shadowed eeprom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 lower memory register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 table 01h register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 table 02h register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 table 04h register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 table 05h register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 table 06h register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 table 07h register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 table 08h register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 auxiliary a0h memory register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 lower memory register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 table 01h register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 table 02h register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 table 04h register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 table 06h register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 table 07h register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 table 08h register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 auxiliary memory a0h register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 applications information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 power-supply decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 sda and scl pullup resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 table of contents (continued) sfp+ controller with analog ldd interface
ds1873 sfp+ controller with analog ldd interface 4 _______________________________________________________________________________________ figure 1. power-up timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 figure 2. txd timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 figure 3. apc loop and quick-trip sample timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 figure 4. adc round-robin timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 figure 5. mon3 differential input for high-side rssi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 figure 6. rssi flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 figure 7. rssi with crossover enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 figure 8. rssi with crossover disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 figure 9. low-voltage hysteresis example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 figure 10. recommended rc filter for dac1/dac2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 figure 11. 3-bit delta-sigma example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 figure 12. mod, dac1, and dac2 offset luts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 figure 13. logic diagram 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 figure 14. logic diagram 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 figure 15a. txf nonlatched operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 figure 15b. txf latched operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 figure 16. i 2 c timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 figure 17. example i 2 c timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 figure 18. memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 table 1. acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 table 2. adc default monitor full-scale ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 table 3. mon3 hysteresis threshold values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 table 4. mon3 configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 list of figures list of tables
ds1873 stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. voltage range on mon1?on4, rsel, in1, los, txf, and txd pins relative to ground .................................-0.5v to (v cc + 0.5v)* voltage range on v cc , sda, scl, out1, rselout, and losout pins relative to ground..............................................-0.5v to +4.2v operating temperature range ...........................-40? to +95? programming temperature range .........................0? to +95? storage temperature range .............................-55? to +125? soldering temperature...........................refer to the ipc/jedec j-std-020 specification. parameter symbol conditions min typ max units main supply voltage v cc (note 1) +2.85 +3.9 v high-level input voltage (sda, scl) v ih:1 0.7 x v cc v cc + 0.3 v low-level input voltage (sda, scl) v il:1 -0.3 0.3 x v cc v high-level input voltage (txd, txf, rsel, in1, los) v ih:2 2.0 v cc + 0.3 v low-level input voltage (txd, txf, rsel, in1, los) v il:2 -0.3 +0.8 v dc electrical characteristics (v cc = +2.85v to +3.9v, t a = -40? to +95?, unless otherwise noted.) * subject to not exceeding +4.2v. recommended operating conditions (t a = -40? to +95?, unless otherwise noted.) absolute maximum ratings sfp+ controller with analog ldd interface _______________________________________________________________________________________ 5 parameter symbol conditions min typ max units supply current i cc (notes 1, 2) 2.5 10 ma output leakage (sda, out1, rselout, losout, txf) i lo 1 a i ol = 4ma 0.4 low-level output voltage (sda, mod, bias, out1, rselout, losout, txdout, dac1, dac2, txf) v ol i ol = 6ma 0.6 v high-level output voltage (mod, bias, dac1, dac2, txdout) v oh i oh = 4ma v cc - 0.4 v txdout before eeprom recall see figure 13 10 100 na mod, bias, dac1, and dac2 before lut recall see figure 12 10 100 na input leakage current (scl, txd, los, rsel, in1) i li 1 a digital power-on reset pod 1.0 2.2 v analog power-on reset poa 2.0 2.75 v
ds1873 sfp+ controller with analog ldd interface 6 _______________________________________________________________________________________ parameter symbol conditions min typ max units adc resolution 13 bits input/supply accuracy (mon1Cmon4, v cc ) acc at factory setting 0.25 0.50 %fs update rate for temperature, mon1Cmon4, and v cc t rr 64 75 ms input/supply offset (mon1Cmon4, v cc ) v os (note 3) 0 5 lsb mon1Cmon4 2.5 v cc 6.5536 v factory setting mon3 fine (note 4) 312.5 v analog voltage monitoring characteristics (v cc = +2.85v to +3.9v, t a = -40? to +95?, unless otherwise noted.) parameter symbol conditions min typ max units mon2, txp hi, txp lo full- scale voltage v apc 2.5 v hbias los full-scale voltage 1.25 v mon2 input resistance 35 50 65 k resolution 8 bits error t a = +25c 2 %fs integral nonlinearity -1 +1 lsb differential nonlinearity -1 +1 lsb temperature drift -2.5 +2.5 %fs los offset -5 mv analog quick trip characteristics (v cc = +2.85v to +3.9v, t a = -40? to +95?, unless otherwise noted.) parameter symbol conditions min typ max units main oscillator freq uency f osc 5 mhz delta-sigma input-clock frequency f ds f osc /2 mhz reference voltage input (refin) v refin minimum 0.1f to gnd 2 v cc v output range 0 v refin v output resolution 10 bits output impedance r ds 35 100 mod, bias, dac1, dac2 electrical characteristics (v cc = +2.85v to +3.9v, t a = -40? to +95?, unless otherwise noted.)
ds1873 parameter symbol conditions min typ max units output-enable time following poa t init (note 5) 20 ms binary search time t search (note 9) 8 10 bias samples sfp+ controller with analog ldd interface _______________________________________________________________________________________ 7 parameter symbol conditions min typ max units txd enable t off from txd to bias dac and mod dac disable 5 s recovery from txd disable (figure 13) t on from txd to bias dac and mod dac enable 5 s recovery after power-up t init_dac from v cc > vcc lo alarm (note 5) 20 ms t initr1 from txd 131 fault reset time (to txf = 0) t initr2 from v cc > vcc lo alarm (note 5) 161 ms fault assert time (to txf = 1) t fault after htxp, ltxp, hbath, ibiasmax (note 6) 15 s losout assert time t loss_on llos (notes 6, 7) 15 s losout deassert time t loss_off hlos (notes 6, 8) 15 s timing characteristics (control loop and quick trip) (v cc = +2.85v to +3.9v, t a = -40? to +95?, unless otherwise noted.) ac electrical characteristics (v cc = +2.85v to +3.9v, t a = -40? to +95?, unless otherwise noted.) parameter symbol conditions min typ max units thermometer error t err -40c to +95c -3 +3 c digital thermometer characteristics (v cc = +2.85v to +3.9v, t a = -40? to +95?, unless otherwise noted.)
note 1: all voltages are referenced to ground. current into the ic is positive, and current out of the ic is negative. note 2: inputs are at supply rail. outputs are not loaded. note 3: this parameter is guaranteed by design. note 4: full-scale is user programmable. note 5: a temperature conversion is completed and the mod dac value is recalled from the lut and v cc has been measured to be above vcc lo alarm. note 6: the sampling time is 1.6? per cycle. each input is sampled every 8 cycles. note 7: this specification is the time it takes from mon3 voltage falling below the llos trip threshold to losout asserted high. note 8: this specification is the time it takes from mon3 voltage rising above the hlos trip threshold to losout asserted low. note 9: assuming an appropriate initial step is programmed that would cause the power to exceed the apc set point within four steps, the bias output will be within 3% within the time specified by the binary search time. see the bias and mod output control during power-up section. note 10: i 2 c interface timing shown is for fast mode (400khz). this device is also backward compatible with i 2 c standard mode timing. note 11: c b ?he total capacitance of one bus line in pf. note 12: eeprom write begins after a stop condition occurs. parameter symbol conditions min typ max units scl clock frequency f scl (note 10) 0 400 khz clock pulse-width low t low 1.3 s clock pulse-width high t high 0.6 s bus-free time between stop and start condition t buf 1.3 s start hold time t hd:sta 0.6 s start setup time t su:sta 0.6 s data out hold time t hd:dat 0 0.9 s data in setup time t su:dat 100 ns rise time of both sda and scl signals t r (note 11) 20 + 0.1c b 300 ns fall time of both sda and scl signals t f (note 11) 20 + 0.1c b 300 ns stop setup time t su:sto 0.6 s eeprom write time t wr (note 12) 20 ms capacitive load for each bus line c b 400 pf ds1873 sfp+ controller with analog ldd interface 8 _______________________________________________________________________________________ nonvolatile memory characteristics (v cc = +2.85v to +3.9v, unless otherwise noted.) parameter symbol conditions min typ max units at +25c 200,000 eeprom write cycles at +85c 50,000 i 2 c ac electrical characteristics (v cc = +2.85v to +3.9v, t a = -40? to +95?, timing referenced to v il(max) and v ih(min) , unless otherwise noted.) (see figure 16.)
ds1873 sfp+ controller with analog ldd interface _______________________________________________________________________________________ 9 typical operating characteristics (v cc = +2.85v to +3.9v, t a = +25?, unless otherwise noted.) supply current vs. supply voltage ds1873 toc01 v cc (v) supply current (ma) 3.75 3.45 3.15 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.1 2.85 sda = scl = v cc +95c +25c -40c supply current vs. temperature ds1873 toc02 temperature (c) supply current (ma) 60 35 10 -15 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.1 -40 85 sda = scl = v cc v cc = 3.9v v cc = 2.8v v cc = 3.3v dac1 and dac2 dnl ds1873 toc03 dac1 and dac2 position (dec) dac1 and dac2 dnl (lsb) 1000 800 600 400 200 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0 dac1 and dac2 inl ds1873 toc04 dac1 and dac2 position (dec) dac1 and dac2 inl (lsb) 1000 800 600 400 200 -2 -1 0 1 2 3 -3 0 mon1 to mon4 inl ds1873 toc05 mon1 to mon4 input voltage (v) mon1 to mon4 inl (lsb) 2.0 1.5 1.0 0.5 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0 2.5 using factory programmed full-scale value of 2.5v mon1 to mon4 dnl ds1873 toc06 mon1 to mon4 input voltage (v) mon1 to mon4 dnl (lsb) 2.0 1.5 1.0 0.5 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0 2.5 using factory programmed full-scale value of 2.5v dac settling time (40% to 60%) ds1873 toc07 time ( s) dac output 1.0193ms 67.7% of peak dac settling time (60% to 40%) ds1873 toc08 time ( s) dac output 990.4s 33.3% of low
ds1873 sfp+ controller with analog ldd interface 10 ______________________________________________________________________________________ pin description pin name function 1 rselout open-drain rate-select output 2 scl i 2 c serial-clock input 3 sda i 2 c serial-data input/output 4 txf transmit-fault input and output. the output is open drain. 5 los loss-of-signal input 6 in1 digital input. general-purpose input with as1 in sff-8079 or rs1 in sff-8431. 7 txd transmit-disable input 8, 18, 21 gnd ground connection 9 rsel rate-select input 10 txdout transmit-disable output 11 mon4 external monitor input 4 12, 13 mon3p, mon3n differential external monitor input 3 and los lo quick trip 14 mon1 external monitor input 1 and hbath quick trip 15, 23 n.c. no connection 16, 26 v cc power-supply input 17 mon2 external monitor input 2. feedback voltage for apc loop and htxp/ltxp quick trip. 19 mod mod dac, delta-sigma output 20 bias bias dac, delta-sigma output 22 refin reference input for dac1 and dac2 24, 25 dac1, dac2 delta-sigma output 1/2 27 losout open-drain receive loss-of-signal output 28 out1 open-drain digital output. general-purpose output with as1 output in sff-8079 or rs1 output in sff-8431. ep exposed pad (connect to gnd) typical operating characteristics (continued) (v cc = +2.85v to +3.9v, t a = +25?, unless otherwise noted.) dac output ripple at 0001h ds1873 toc09 time (100 s/div) 0.68mv filter output dac2 output dac position = 0001h 3v/div dac output ripple at 3fffh ds1873 toc10 time (100 s/div) 0.1mv dac2 output dac position = 3fffh 3v/div filter output
ds1873 sfp+ controller with analog ldd interface ______________________________________________________________________________________ 11 block diagram analog mux main memory eeprom/sram adc configuration/results, system status/control bits, alarms/warnings, lookup tables, user memory i 2 c interface temperature sensor apc integrator logic control power-on analog interrupt 13-bit adc eeprom 256 bytes at a0h sda scl v cc v cc v cc mon1 mon2 mon4 txd mon3p mon3n logic control dac1 10 bits dac2 10 bits 8-bit qts dac1 dac2 mod dac 10 bits mod bias dac 10 bits bias txf refin txdout rselout out1 losout rsel in1 los gnd ds1873 v cc
ds1873 sfp+ controller with analog ldd interface 12 ______________________________________________________________________________________ los txf txd txdout disable bias mon los losout tx_fault sda scl mode_def2 (sda) los mode_def1 (scl) tx_disable mod dac bias dac ldd eeprom quick trip los adc i 2 c ds1873 mon1 mon2 mon3 r mon 100 +3.3v r bd rosa tosa detailed description the ds1873 integrates the control and monitoring func- tionality required to implement an sfp or sfp+ system. key components of the ds1873 are shown in the block diagram and described in subsequent sections. bias dac/apc control the ds1873 controls its laser bias current using its bias dac and the apc loop. the apc loop? feedback to the ds1873 is the monitor diode (mon2) current, which is converted to a voltage using an external resis- tor. the feedback is sampled by a comparator and compared to a digital set-point value. the output of the comparator has three states: up, down, or no-opera- tion. the no-operation state prevents the output from excessive toggling once steady state is reached. as long as the comparator output is in either the up or down states, the bias is adjusted by incrementing and decrementing the bias dac setting. the ds1873 has an lut to allow the apc set point to change as a function of temperature to compensate for tracking error (te). the te lut has 36 entries that determine the apc setting in 4? windows between -40? to +100?. typical operating circuit
ds1873 sfp+ controller with analog ldd interface ______________________________________________________________________________________ 13 bias and mod output control during power-up on power-up, the ds1873 sets the mod and bias dacs to 0. after a temperature conversion is complet- ed and if the vcc lo alarm is enabled, an additional v cc conversion above the customer-defined vcc lo alarm level is required before the mod dac is updated with the value determined by the temperature conver- sion and the modulation lut. when the mod dac is set, the bias dac is set to a value equal to istep (see figure 1). the startup algo- rithm checks if this bias current causes a feedback voltage above the apc set point, and if not, it continues increasing the bias dac by istep until the apc set- point is exceeded. when the apc set point is exceed- ed, the device begins a binary search to quickly reach the bias current corresponding to the proper power level. after the binary search is completed, the apc integrator is enabled and single lsb steps are used to tightly control the average power. the txp hi, txp lo, hbal, and bias max qt alarms are masked until the binary search is completed. however, the bias max alarm is monitored during this time to prevent the bias dac from exceeding ibiasmax. during the bias current initialization, the bias dac is not allowed to exceed ibiasmax. if this occurs during the istep sequence, then the binary search routine is table 1. acronyms acronym definition adc analog-to-digital converter agc automatic gain control apc automatic power control apd avalanche photodiode atb alarm trap bytes bm burst mode dac digital-to-analog converter los loss of signal lut lookup table nv nonvolatile qt quick trip te tracking error tia transimpedance amplifier rosa receiver optical subassembly see shadowed eeprom sff small form factor sff-8472 document defining register map of sfps and sffs sfp small form factor pluggable sfp+ enhanced sfp tosa transmit optical subassembly txp transmit power 12345678910111213 v poa mod dac bias dac v cc bias sample t init t search binary search apc integrator on 4x istep 3x istep 2x istep istep figure 1. power-up timing
ds1873 sfp+ controller with analog ldd interface 14 ______________________________________________________________________________________ enabled. if ibiasmax is exceeded during the binary search, the next smaller step is activated. istep or binary increments that would cause the bias dac to exceed ibiasmax are not taken. masking the alarms until the completion of the binary search prevents false positive alarms during startup. istep is programmed by the customer using table 02h, register bbh. istep should be programmed to the maximum safe increase that is allowable during startup. if this value is programmed too low, the ds1873 still operates, but it could take significantly longer for the algorithm to converge and hence to con- trol the average power. if a fault is detected, and txd is toggled to reenable the outputs, the ds1873 powers up following a similar sequence to an initial power-up. the only difference is that the ds1873 already has determined the present temperature, so the t init time is not required for the ds1873 to recall the apc and mod set points from eeprom. bias and mod dacs as a function of transmit disable (txd) if txd is asserted (logic 1) during normal operation, the outputs are disabled within t off . when txd is deasserted (logic 0), the ds1873 sets the mod dac register with the value associated with the present tem- perature, and initializes the bias dac using the same search algorithm as done at startup. when asserted, soft txd (txdc) (lower memory, register 6eh) would allow a software control identical to the txd pin (see figure 2). apc and quick-trip timing as shown in figure 3, the ds1873? input comparator is shared between the apc control loop and the quick-trip alarms (txp hi, txp lo, los lo, and bias hi). the comparator polls the alarms in a multiplexed sequence. five of every eight comparator readings are used for apc loop bias-current control. the other three updates are used to check the htxp/ltxp (monitor diode volt- age), the hbath (mon1), and los (mon3) signals against the internal apc, bias, and mon3 reference, respectively. if the last apc comparison was higher than the apc set point, it makes an htxp comparison, and if it is lower, it makes an ltxp comparison. depending on the results of the comparison, the corre- sponding alarms and warnings (txp hi, txp lo) are asserted or deasserted. the ds1873 has a programmable comparator sample time based on an internally generated clock to facilitate a wide variety of external filtering options and time delays. the update rate register (table 02h, register 88h) determines the sampling time. samples occur at a regular interval, t rep , which is set at 1.6?. table 2 shows the sample rate options available. any quick-trip alarm that is detected by default remains active until a subsequent comparator sample shows the condition no longer exists. a second bias current monitor (bias max) compares the bias dac? code to a digital value stored in the ibiasmax register. this comparison is made at every bias current update to ensure that a high-bias current is quickly detected. the quick-trip comparator uses a 1.6s window to sam- ple each input. after an apc comparison that requires apc quick-trip sample times hbias sample hbias sample los sample apc sample apc sample apc sample apc sample apc sample apc sample htxp/ltxp sample t rep figure 3. apc loop and quick-trip sample timing t off t off t on t on txd bias dac mod dac setting figure 2. txd timing
ds1873 sfp+ controller with analog ldd interface ______________________________________________________________________________________ 15 an update to the bias dac, a settling time (as calculat- ed below) is required to allow for the feedback on bmd (mon2) to stabilize. this time is dependent on the time constant of the filter pole used for the delta-to-sigma bias output. during the timing of the settling rate, com- parisons of apc comparisons of bmd are ignored until 32 sample periods (t rep ) have passed. settlingtime = 51.2? x (apc_sr[3:0] + 1) monitors and fault detection monitors monitoring functions on the ds1873 include five quick- trip comparators and six adc channels. this monitor- ing combined with the alarm enables (table 01h/05h) determines when/if the ds1873 turns off the mod and bias dacs and triggers the txf and txdout outputs. all the monitoring levels and interrupt masks are user programmable. five quick-trip monitors and alarms five quick-trip monitors are provided to detect potential laser safety issues and los status. these monitor the following: 1) high bias current (hbath) 2) low transmit power (ltxp) 3) high transmit power (htxp) 4) max output current (ibiasmax) 5) loss-of-signal (los lo) the high-transmit and low-transmit power quick-trip registers (htxp and ltxp) set the thresholds used to compare against the mon2 voltage to determine if the transmit power is within specification. the hbath quick trip compares the mon1 input (generally from the laser driver? bias monitor output) against its threshold setting to determine if the present bias current is above specification. the bias max quick trip determines if the bias dac is above specification (ibiasmax). when the new bias dac value is calculated, it is compared against the ibiasmax register. the bias dac is not allowed to exceed the value set in the ibiasmax regis- ter. when the ds1873 detects that the bias is at the limit, it sets the biasmax status bit and holds the bias dac setting at the ibiasmax level. the bias and power quick trips are routed to the txf through interrupt masks to allow combinations of these alarms to be used to trigger these outputs. the user can program up to eight different temperature-indexed threshold levels for mon1 (table 02h, register d1h). the los lo quick trip compares the mon3 input against its threshold set- ting to determine if the present received power is below the specification. the los lo quick trip can be used to set the losout pin. six adc monitors and alarms the adc monitors six channels that measure tempera- ture (internal temp sensor), v cc , and mon1?on4 using an analog multiplexer to measure them round robin with a single adc (see the adc timing section). the five voltage channels have a customer-programma- ble full-scale range and all channels have a customer- programmable offset value that is factory programmed to default value (see table 2). additionally, mon1?on4 can right-shift results by up to 7 bits before the results are compared to alarm thresholds or read over the i 2 c bus. this allows customers with speci- fied adc ranges to calibrate the adc full scale to a fac- tor of 1/2 n of their specified range to measure small signals. the ds1873 can then right-shift the results by n bits to maintain the bit weight of their specification (see the right-shifting adc result and enhanced rssi monitoring (dual-range functionality) sections). the adc results (after right-shifting, if used) are com- pared to the alarm and warning thresholds after each conversion, and the corresponding alarms are set, which can be used to trigger the txf output. these adc thresholds are user programmable, as are the masking registers that can be used to prevent the alarms from triggering the txf output. adc timing there are six analog channels that are digitized in a round-robin fashion in the order shown in figure 4. the total time required to convert all six channels is t rr (see the analog voltage monitoring characteristics for details). right-shifting adc result if the weighting of the adc digital reading must con- form to a predetermined full-scale (pfs) value defined by a standard? specification (e.g., sff-8472), then right-shifting can be used to adjust the pfs analog measurement range while maintaining the weighting of table 2. adc default monitor full-scale ranges signal +fs signal +fs hex -fs signal -fs hex temperature (c) 127.996 7fff -128 8000 v cc (v) 6.5528 fff8 0 0000 mon1Cmon4 (v) 2.4997 fff8 0 0000
ds1873 sfp+ controller with analog ldd interface 16 ______________________________________________________________________________________ temp v cc mon1 mon2 mon3 mon4 temp one round-robin adc cycle t rr note: if the vcc lo alarm is enabled at power-up, the adc round-robin timing cycles between temperature and v cc only until v cc is above the v cc alarm low threshold. the adc results. the ds1873? range is wide enough to cover all requirements; when the maximum input value is 1/2 of the fs value, right-shifting can be used to obtain greater accuracy. for instance, the maximum voltage might be 1/8 the specified pfs value, so only 1/8 the converter? range is effective over this range. an alternative is to calibrate the adc? full-scale range to 1/8 the readable pfs value and use a right-shift value of 3. with this implementation, the resolution of the measurement is increased by a factor of 8, and because the result is digitally divided by 8 by right- shifting, the bit weight of the measurement still meets the standard? specification (i.e., sff-8472). the right-shift operation on the adc result is carried out based on the contents of right-shift control registers (table 02h, registers 8dh?fh) in eeprom. four ana- log channels, mon1?on4, each have 3 bits allocated to set the number of right-shifts. up to 7 right-shift oper- ations are allowed and are executed as a part of every conversion before the results are compared to the high- alarm and low-alarm levels, or loaded into their corre- sponding measurement registers (lower memory, registers 64h?bh). this is true during the setup of internal calibration as well as during subsequent data conversions. differential mon3 input the ds1873 offers a fully differential input for mon3. this enables high-side monitoring of rssi, as shown in figure 5. this reduces board complexity by eliminating the need for a high-side differential amplifier or a cur- rent mirror. enhanced rssi monitoring (dual-range functionality) the ds1873 offers a feature to improve the accuracy and range of mon3, which is most commonly used for monitoring rssi. the accuracy of the rssi measure- ments is increased at the small cost of reduced range (of input signal swing). the ds1873 eliminates this trade-off by offering ?ual range?calibration on the mon3 channel (see figure 5). this feature enables right-shifting (along with its gain and offset settings) when the input signal is below a set threshold (within the range that benefits using right-shifting) and then automat- ically disables right-shifting (recalling different gain and offset settings) when the input signal exceeds the thresh- old. also, to prevent ?hattering,?hysteresis prevents excessive switching between modes in addition to ensur- ing that continuity is maintained. dual-range operation is enabled by default (factory programmed in eeprom). however, it can easily be disabled through the rssi_fc and rssi_ff bits, which are described in the register descriptions section. when dual-range operation is dis- abled, mon3 operates identically to the other mon channels, although featuring a differential input. dual-range functionality consists of two modes of opera- tion: fine mode and coarse mode. each mode is calibrat- ed for a unique transfer function, hence the term, dual range. table 4 highlights the registers related to mon3. fine mode is equivalent to the other mon channels. fine mode is calibrated using the gain, offset, and right-shift- ing registers at locations shown in table 4 and is ideal for relatively small analog input voltages. coarse mode is automatically switched to when the input exceeds a threshold (to be discussed in a subsequent paragraph). coarse mode is calibrated using different gain and offset registers, but lacks right-shifting (since coarse mode is only used on large input signals). the gain and offset registers for coarse mode are also shown in table 4. ds1873 mon3p mon3n adc 100 rosa v cc figure 5. mon3 differential input for high-side rssi figure 4. adc round-robin timing
ds1873 sfp+ controller with analog ldd interface ______________________________________________________________________________________ 17 additional information for each of the registers can be found in the register descriptions section. dual-range operation is transparent to the end user. the results of mon3 analog-to-digital conversions are still stored/reported in the same memory locations (68h?9h, lower memory) regardless of whether the conversion was performed in fine mode or coarse mode. the only way to tell which mode generated the digital result is by reading the rssir bit. when the ds1873 is powered up, analog-to-digital con- versions begin in a round-robin fashion. every mon3 timeslice begins with a fine mode analog-to-digital con- version (using fine mode? gain, offset, and right-shifting settings). see the flowchart in figure 6 for more details. then, depending on whether the last mon3 timeslice resulted in a coarse-mode conversion and also depend- ing on the value of the current fine conversion, decisions are made whether to use the current fine-mode conver- sion result or to make an additional conversion (within the same mon3 timeslice), using coarse mode (using coarse mode? gain and offset settings and no right- shifting) and reporting the coarse-mode result. the flow- chart in figure 6 also illustrates how hysteresis is implemented. the fine-mode conversion is compared to one of two thresholds. the actual threshold values are a function of the number of right-shifts being used. with the use of right-shifting, the fine mode full-scale is pro- grammed to (1/2 n th) of the coarse mode full-scale. the ds1873 now auto ranges to choose the range that gives the best resolution for the measurement. hysteresis is applied to eliminate chatter when the input resides at the boundary of the two ranges. see figure 6 for details. table 3 shows the threshold values for each possible number of right-shifts. table 4. mon3 configuration registers register fine mode coarse mode gain 98hC99h, table 02h 9chC9dh, table 02h offset a8hCa9h, table 02h achCadh, table 02h right-shift 0 8fh, table 02h cnfgc 8bh, table 02h update (rssir bit) 6fh, lower memory mon3 value 68hC69h, lower memory number of right-shifts fine mode max (hex) coarse mode min* (hex) 0 fff8 f000 1 7ffc 7800 2 3ffe 3c00 3 1fff 1e00 4 0fff 0f00 5 07ff 0780 6 03ff 03c0 7 01ff 01e0 mon3 timeslice end of mon3 timeslice perform fine- mode conversion report fine conversion result report coarse conversion result did prior mon3 timeslice result in a coarse conversion? (last rssir = 1?) last rssir = 0 last rssir = 1 was current fine- mode conversion 93.75% of fs? perform coarse- mode conversion did current fine- mode conversion reach max? n y y y n n figure 6. rssi flowchart table 3. mon3 hysteresis threshold values * this is the minimum reported coarse-mode conversion.
ds1873 sfp+ controller with analog ldd interface 18 ______________________________________________________________________________________ the rssi_ff and rssi_fc bits are used to force fine- mode or coarse-mode conversions, or to disable the dual-range functionality. dual-range functionality is enabled by default (both rssi_fc and rssi_ff are factory programmed to 0 in eeprom). it can be dis- abled by setting rssi_fc to 0 and rssi_ff to 1. these bits are also useful when calibrating mon3. for addi- tional information, see figure 18. the dual-range cali- bration can operate in two modes: crossover enabled and crossover disabled. crossover enabled: for systems with nonlinear relationships between the adc input and the desired adc result, the mode should be set to crossover enabled. the rssi measurement of an apd receiver is one such application. using the crossover- enabled mode allows a piecewise linear approxima- tion of the nonlinear response of the apd? gain fac- tor. the crossover point is the point between fine and coarse points. the adc result transitions between the fine and coarse ranges with no hysteresis. right- shifting, slope adjustment, and offset are config- urable for both the fine and coarse ranges. see figure 7. crossover disabled: the crossover-disabled mode is intended for systems with a linear relationship between the mon3 input and the desired adc result. hysteresis allows for a nonjittery response when the input is at the crossover boundary of the fine and coarse adc. in a nonlinear system, the hys- teresis could cause significant errors in the adc result. see figure 8. rssi result fine full-scale response coarse full-scale response fine right-shift = 3 mon3 input fine coarse hysteresis figure 8. rssi with crossover disabled crossover point rssi result ideal response mon3 input figure 7. rssi with crossover enabled
ds1873 sfp+ controller with analog ldd interface ______________________________________________________________________________________ 19 v poa v pod v cc see recalled value recalled value precharged to 0 precharged to 0 precharged to 0 see recall see recall figure 9. low-voltage hysteresis example low-voltage operation the ds1873 contains two power-on reset (por) levels. the lower level is a digital por (pod) and the higher level is an analog por (poa). at startup, before the supply voltage rises above poa, the outputs are dis- abled, all sram locations are set to their defaults, shadowed eeprom (see) locations are zero, and all analog circuitry is disabled. when v cc reaches poa, the see is recalled, and the analog circuitry is enabled. while v cc remains above poa, the device is in its nor- mal operating state, and it responds based on its non- volatile configuration. if during operation v cc falls below poa, but is still above pod, then the sram retains the see settings from the first see recall, but the device analog is shut down and the outputs disabled. if the supply voltage recovers back above poa, then the device immediately resumes normal operation. if the supply voltage falls below pod, then the device sram is placed in its default state and another see recall is required to reload the nonvolatile settings. the eep- rom recall occurs the next time v cc exceeds poa. figure 9 shows the sequence of events as the voltage varies. any time v cc is above pod, the i 2 c interface can be used to determine if v cc is below the poa level. this is accomplished by checking the rdyb bit in the status (lower memory, register 6eh) byte. rdyb is set when v cc is below poa; when v cc rises above poa, rdyb is timed (within 500?) to go to 0, at which point the part is fully functional. for all device addresses sourced from eeprom (table 02h, register 8ch), the default device address is a2h until v cc exceeds poa, allowing the device address to be recalled from the eeprom. power-on analog (poa) poa holds the ds1873 in reset until v cc is at a suitable level (v cc > poa) for the device to accurately measure with its adc and compare analog signals with its quick- trip monitors. because v cc cannot be measured by the adc when v cc is less than poa, poa also asserts the vcc lo alarm, which is cleared by a v cc adc conver- sion greater than the customer-programmable v cc alarm lo adc limit. this allows a programmable limit to ensure that the headroom requirements of the trans- ceiver are satisfied during a slow power-up. the txf output does not latch until there is a conversion above v cc low limit. the poa alarm is nonmaskable. the txf output is asserted when v cc is below poa. see the low-voltage operation section for more information. delta-sigma outputs four delta-sigma outputs are provided: mod dac, bias dac, dac1, and dac2. with the addition of an external rc filter, these outputs provide 10-bit resolu- tion analog outputs with the full-scale range set by the input refin. each output is either manually controlled or controlled using a temperature-indexed lut, or in the case of the bias dac, controlled by the apc loop. a delta-sigma is a digital output using pulse-density modulation. it provides much lower output ripple than a
ds1873 sfp+ controller with analog ldd interface 20 ______________________________________________________________________________________ standard digital pwm output given the same clock rate and filter components. before t init , the dac outputs are high impedance. the external rc filter components are chosen based on ripple requirements, output load, delta-sigma fre- quency, and desired response time. a recommended filter is shown in figure 10. the ds1873? delta-sigma outputs are 10 bits. for illus- trative purposes, a 3-bit example is provided. each possible output of this 3-bit delta-sigma dac is given in figure 11. in lut mode, mod, dac1, and dac2 are each con- trolled by an lut with high-temperature resolution and an offset lut with lower temperature resolution. the mod and dac1 high-resolution luts each have 2? resolution. the dac2 high-resolution lut has 4? reso- lution. the offset luts are located in the upper eight registers (f8h?fh) of the table containing each high- resolution lut. mod dac, dac1 value, and dac2 value are determined as follows: mod dac = mod lut + 4 x (mod offset lut) dac1 value = dac1 lut + 4 x (dac1 offset lut) dac2 value = dac1 lut + 4 x (dac1 offset lut) example calculation for mod dac: assumptions: 1) temperature is 43?. 2) table 04h (mod offset lut), register fch = 2ah. 3) table 04h (mod lut), register a9h = 7bh. because the temperature is 43?, the mod lut index is a9h and the mod offset lut index is fch. mod dac = 7bh + 4 x 2ah = 123h = 291 when temperature controlled, the dacs are updated after each temperature conversion. the reference input, refin, is the supply voltage for all four dacs. the voltage connected to refin and its decoupling must be able to support the edge rate requirements of the delta-sigma outputs. ds1873 dac 3.24k 3.24k 0.01f 0.01f output 1 2 3 4 5 6 7 0 figure 11. 3-bit delta-sigma example figure 10. recommended rc filter for dac1/dac2
ds1873 sfp+ controller with analog ldd interface ______________________________________________________________________________________ 21 mod, dac1, and dac2 offset luts (04h, 07h, and 08h) eight registers per dac 0 255 511 delta-sigma mod, dac1, and dac2 767 1023 each offset register can be independently set between 0 and 1020. 1020 = 4 x ffh. this example illustrates positive and negatve tempco. dac lut bits 7:0 f8h dac lut bits 7:0 f9h dac lut bits 7:0 fah dac lut bits 7:0 fbh dac lut bits 7:0 fch dac lut bits 7:0 fdh dac lut bits 7:0 feh dac lut bits 7:0 ffh 0 255 511 -40 c-8 c+8 c +24 c +40 c +56 c +70 c +88 c +104c delta-sigma mod, dac1, and dac2 767 1023 each offset register can be independently set between 0 and 1020. 1020 = 4 x ffh. this example illustrates positive tempco. dac lut bits 7:0 f8h dac lut bits 7:0 f9h dac lut bits 7:0 fah dac lut bits 7:0 fbh dac lut bits 7:0 fch dac lut bits 7:0 fdh dac lut bits 7:0 feh dac lut bits 7:0 ffh mod, dac1, and dac2 offset luts (04h, 07h, and 08h) eight registers per dac -40 c-8 c+8 c +24 c +40 c +56 c +70 c +88 c +104c figure 12. mod, dac1, and dac2 offset luts digital i/o pins five digital input and five digital output pins are provid- ed for monitoring and control. los, losout by default (losc = 1, table 02h, register 89h), the los pin is used to convert a standard comparator out- put for loss of signal (los) to an open-collector output. this means the mux shown in the block diagram by default selects the los pin as the source for the losout output transistor. the output of the mux can be read in the status byte (lower memory, register 6eh) as the rxl bit. the rxl signal can be inverted (inv los = 1) before driving the open-drain output transistor using the xor gate provided. setting losc = 0 configures the mux to be controlled by los lo, which is driven by the output of the los quick trip (table 02h, registers beh and bfh). the mux setting (stored in eeprom) does not take effect until v cc > poa, allowing the eeprom to recall. in1, rsel, out1, rselout the digital input in1 and rsel pins primarily serve to meet the rate-select requirements of sfp and sfp+. they also serve as general-purpose inputs. out1 and rselout are driven by a combination of the in1, rsel, and logic dictated by control registers in the eeprom (figure 14). the levels of in1 and rsel can be read using the status register (lower memory, register 6eh). the open-drain output out1 can be controlled and/or inverted using the cnfgb register (table 02h, register 8ah). the open-drain rselout output is software-controlled and/or inverted through the status register and cnfga register (table 02h, register 89h). external pullup resistors must be provid- ed on out1 and rselout to realize high logic levels.
ds1873 sfp+ controller with analog ldd interface 22 ______________________________________________________________________________________ txf, txd, txdout txdout is generated from a combination of txf, txd, and the internal signal fetg. a software control identical to txd is available (txdc, lower memory, register 6eh). a txd pulse is internally extended (txd ext ) by time t initr1 to inhibit the latching of low alarms and warnings related to the apc loop to allow for the loop to stabilize. the nonlatching alarms and warnings are txp lo, los lo, and mon1?on4 lo alarms and warn- ings. in addition, txp lo is disabled from creating fetg. txf is both an input and an output (figure 13). see the transmit fault (txf) output section for a detailed expla- nation of txf. figure 13 shows that the same signals and faults can also be used to generate the internal signal fetg (table 01h/05h, registers fah and fbh). fetg is used to send a fast ?urn-off?command to the laser dri- ver. the intended use is a direct connection to the laser driver? txd input if this is desired. when v cc < poa, txdout is high impedance. invout1 in1c in1 in1s out1 inv los losc mux losout rselout rselc rsel los los lo rsels rxl = pins figure 14. logic diagram 2 c c d q q s r out in txds r pu txf set bias dac and mod dac to 0 txd mint hbal flag txp lo flag txp hi flag bias max flag txp hi flag txp hi enable bias max bias max enable hbal flag hbal enable txp lo flag txp lo enable txd ext txdc = pins v cc txd txf txdout txdio txdfg fetg txdflt fault reset timer (130ms) in out power-on reset figure 13. logic diagram 1
ds1873 sfp+ controller with analog ldd interface ______________________________________________________________________________________ 23 transmit fault (txf) output txf can be triggered by all alarms, warnings, and quick trips (figure 13). the six adc alarms, warnings, and the los quick trips require enabling (table 01h/05h, registers f8h and fdh). see figures 15a and 15b for nonlatched and latched operation. latching of the alarms is controlled by the cnfgb and cnfgc registers (table 02h, registers 8ah?bh). die identification the ds1873 has an id hardcoded in its die. two regis- ters (table 02h, registers ceh?fh) are assigned for this feature. the ceh register reads 73h to identify the part as the ds1873, while the cfh register reads the current device version. i 2 c communication i 2 c definitions the following terminology is commonly used to describe i 2 c data transfers. master device: the master device controls the slave devices on the bus. the master device gen- erates scl clock pulses and start and stop conditions. slave devices: slave devices send and receive data at the master? request. bus idle or not busy: time between stop and start conditions when both sda and scl are inac- tive and in their logic-high states. start condition: a start condition is generated by the master to initiate a new data transfer with a slave. transitioning sda from high to low while scl remains high generates a start condition. see figure 16 for applicable timing. stop condition: a stop condition is generated by the master to end a data transfer with a slave. transitioning sda from low to high while scl remains high generates a stop condition. see figure 16 for applicable timing. repeated start condition: the master can use a repeated start condition at the end of one data transfer to indicate that it will immediately initiate a new data transfer following the current one. repeated starts are commonly used during read operations to identify a specific memory address to begin a data transfer. a repeated start condition is issued identically to a normal start condition. see figure 16 for applicable timing. detection of txf fault txd or txf reset txf figure 15b. txf latched operation detection of txf fault txf figure 15a. txf nonlatched operation
ds1873 sfp+ controller with analog ldd interface 24 ______________________________________________________________________________________ scl note: timing is referenced to v il(max) and v ih(min) . sda stop start repeated start t buf t hd:sta t hd:dat t su:dat t su:sto t hd:sta t sp t su:sta t high t r t f t low figure 16. i 2 c timing bit write: transitions of sda must occur during the low state of scl. the data on sda must remain valid and unchanged during the entire high pulse of scl plus the setup and hold time requirements (figure 16). data is shifted into the device during the rising edge of the scl. bit read: at the end a write operation, the master must release the sda bus line for the proper amount of setup time (figure 16) before the next rising edge of scl during a bit read. the device shifts out each bit of data on sda at the falling edge of the previous scl pulse and the data bit is valid at the rising edge of the current scl pulse. remember that the master generates all scl clock pulses, including when it is reading bits from the slave. acknowledgement (ack and nack): an acknowl- edgement (ack) or not acknowledge (nack) is always the ninth bit transmitted during a byte trans- fer. the device receiving data (the master during a read or the slave during a write operation) performs an ack by transmitting a zero during the ninth bit. a device performs a nack by transmitting a one dur- ing the 9th bit. timing (figure 16) for the ack and nack is identical to all other bit writes. an ack is the acknowledgment that the device is properly receiving data. a nack is used to terminate a read sequence or as an indication that the device is not receiving data. byte write: a byte write consists of 8 bits of informa- tion transferred from the master to the slave (most significant bit first) plus a 1-bit acknowledgement from the slave to the master. the 8 bits transmitted by the master are done according to the bit-write definition and the acknowledgement is read using the bit-read definition. byte read: a byte read is an 8-bit information trans- fer from the slave to the master plus a 1-bit ack or nack from the master to the slave. the 8 bits of information that are transferred (most significant bit first) from the slave to the master are read by the master using the bit-read definition, and the master transmits an ack using the bit-write definition to receive additional data bytes. the master must nack the last byte read to terminate communication so the slave returns control of sda to the master. slave address byte: each slave on the i 2 c bus responds to a slave address byte sent immediately following a start condition. the slave address byte contains the slave address in the most significant 7 bits and the r/w bit in the least significant bit. the ds1873 responds to two slave addresses. the auxiliary memory always responds to a fixed i 2 c slave address, a0h. the lower memory and tables 00h?8h respond to i 2 c slave addresses that can be configured to any value between 00h?eh using the device address byte (table 02h, register 8ch). the user also must set the asel bit (table 02h, register 89h) for this address to be active. by writing the correct slave address with r/w = 0, the master indicates it will write data to the slave. if r/ w
ds1873 sfp+ controller with analog ldd interface ______________________________________________________________________________________ 25 = 1, the master reads data from the slave. if an incorrect slave address is written, the ds1873 assumes the master is communicating with another i 2 c device and ignores the communications until the next start condition is sent. if the main device? slave address is programmed to be a0h, access to the auxiliary memory is disabled. memory address: during an i 2 c write operation to the ds1873, the master must transmit a memory address to identify the memory location where the slave is to store the data. the memory address is always the second byte transmitted during a write operation following the slave address byte. i 2 c protocol writing a single byte to a slave: the master must generate a start condition, write the slave address byte (r/w = 0), write the memory address, write the byte of data, and generate a stop condition. remember the master must read the slave? acknowledgement during all byte-write operations. writing multiple bytes to a slave: to write multiple bytes to a slave, the master generates a start con- dition, writes the slave address byte (r/ w = 0), writes the memory address, writes up to 8 data bytes, and generates a stop condition. the ds1873 writes 1 to 8 bytes (one page or row) with a single write transaction. this is internally controlled by an address counter that allows data to be written to consecutive addresses without transmitting a memory address before each data byte is sent. the address counter limits the write to one 8-byte page (one row of the memory map). attempts to write to additional pages of memory without sending a stop condition between pages results in the address counter wrapping around to the beginning of the present row. for example, a 3-byte write starts at address 06h and writes three data bytes (11h, 22h, and 33h) to three ?onsecutive?addresses. the result is that addresses 06h and 07h would contain 11h and 22h, respectively, and the third data byte, 33h, would be written to address 00h. to prevent address wrapping from occurring, the master must send a stop condition at the end of the page, then wait for the bus-free or eeprom write time to elapse. then the master can generate a new start condition and write the slave address start start stop slave ack slave ack stop single-byte write -write 00h to register bah two-byte write -write 01h and 75h to c8h and c9h single-byte read -read register bah two-byte read -read c8h and c9h repeated start master nack 10100010 a2h 10111010 bah slave ack start slave ack 10100010 a2h 10100011 a3h 10111010 bah slave ack slave ack stop 00000000 00h stop slave ack stop 01110101 75h start slave ack 10100010 a2h 11001000 c8h slave ack slave ack 00000001 01h slave ack data in bah data repeated start master ack start slave ack 10100010 a2h 10100011 a3h 11001000 c8h slave ack slave ack data in c8h data master nack data in c9h data example i 2 c transactions with a2h as the main memory device address *if asel is 0, the slave address is a0h for the auxiliary memory and a2h for the main memory. if asel = 1, the slave address is determined by table 02h, register 8ch for the main memory. the auxiliary memory continues to be addressed at a0h, except when the programmed address for the main memory is a0h. typical i 2 c write transaction a) c) b) d) msb lsb b7 b6 b5 b4 b3 b2 b1 b0 register address msb lsb b7 b6 b5 b4 b3 b2 b1 b0 data slave ack slave ack slave address* 1 0 1 0 0 0 1 r/w msb lsb read/ write figure 17. example i 2 c timing
ds1873 sfp+ controller with analog ldd interface 26 ______________________________________________________________________________________ byte (r/w = 0) and the first memory address of the next memory row before continuing to write data. acknowledge polling: any time a eeprom page is written, the ds1873 requires the eeprom write time (t w ) after the stop condition to write the contents of the page to eeprom. during the eeprom write time, the ds1873 will not acknowledge its slave address because it is busy. it is possible to take advantage of that phenomenon by repeatedly addressing the ds1873, which allows the next page to be written as soon as the ds1873 is ready to receive the data. the alternative to acknowledge polling is to wait for maximum period of t w to elapse before attempting to write again to the ds1873. eeprom write cycles: when eeprom writes occur, the ds1873 writes the whole eeprom memory page, even if only a single byte on the page was modified. writes that do not modify all 8 bytes on the page are allowed and do not corrupt the remaining bytes of memory on the same page. because the whole page is written, bytes on the page that were not modified during the transaction are still subject to a write cycle. this can result in a whole page being worn out over time by writing a single byte repeatedly. writing a page one byte at a time wears the eeprom out eight times faster than writing the entire page at once. the ds1873? eeprom write cycles are speci- fied in the nonvolatile memory characteristics table. the specification shown is at the worst-case temper- ature. it can handle approximately ten times that many writes at room temperature. writing to sram- shadowed eeprom memory with seeb = 1 does not count as an eeprom write cycle when evaluating the eeprom? estimated lifetime. reading a single byte from a slave: unlike the write operation that uses the memory address byte to define where the data is to be written, the read operation occurs at the present value of the memory address counter. to read a single byte from the slave, the master generates a start condition, writes the slave address byte with r/ w = 1, reads the data byte with a nack to indicate the end of the transfer, and generates a stop condition. manipulating the address counter for reads: a dummy write cycle can be used to force the address pointer to a particular value. to do this, the master generates a start condition, writes the slave address byte (r/w = 0), writes the memory address where it desires to read, generates a repeated start condition, writes the slave address byte (r/w = 1), reads data with ack or nack as applicable, and generates a stop condition. memory organization the ds1873 features nine separate memory tables that are internally organized into 8-byte rows. the ds1873 has two passwords that are each 4 bytes long. the lower level password (pw1) has all the access of a normal user plus those made available with pw1. the higher level password (pw2) has all the access of pw1 plus those made available with pw2. the values of the passwords reside in eeprom inside of pw2 memory. at power-up, all pwe bits are set to 1, and all reads at this location are 0. the lower memory is addressed from 00h to 7fh and contains alarm and warning thresholds, flags, masks, several control registers, password entry area (pwe), and the table-select byte. table 01h primarily contains user eeprom (with pw1 level access) as well as alarm and warning-enable bytes. table 02h is a multifunction space that contains config- uration registers, scaling and offset values, passwords, interrupt registers as well as other miscellaneous con- trol bytes. table 04h contains a temperature-indexed lut for control of the modulation output. the modulation lut can be programmed in 2? increments over the -40? to +102? range. the table also contains a tempera- ture-indexed lut for mod offsets. table 05h is empty by default. it can be configured to contain the alarm- and warning-enable bytes from table 01h, registers f8h?fh with the mask bit enabled (table 02h, register 89h). in this case table 01h is empty. table 06h contains a temperature-indexed lut that allows the apc set point to change as a function of temperature to compensate for tracking error (te). the apc lut has 36 entries that determine the apc setting in 4? windows between -40? and +100?. the table also contains a temperature-indexed lut for hbias thresholds. table 07h contains a temperature-indexed lut for con- trol of dac1. the lut has 72 entries that determine the dac setting in 4? windows between -40? and +100?. the table also contains a temperature-indexed lut for dac1 offsets.
ds1873 sfp+ controller with analog ldd interface ______________________________________________________________________________________ 27 table 08h contains a temperature-indexed lut for control of dac2. the lut has 36 entries that determine the dac setting in 4? windows between -40? and +100?. auxiliary memory (device a0h) contains 256 bytes of ee memory accessible from address 00h?fh. it is selected with the device address of a0h. see the register descriptions section for more com- plete details of each byte? function, as well as for read/write permissions for each byte. shadowed eeprom many nv memory locations (listed within the register descriptions section) are actually shadowed eeprom that are controlled by the seeb bit in table 02h, register 80h. the ds1873 incorporates shadowed-eeprom memory locations for key memory addresses that can be written many times. by default the shadowed-eeprom bit, seeb, is not set and these locations act as ordinary eep- rom. by setting seeb, these locations function like sram cells, which allow an infinite number of write cycles without concern of wearing out the eeprom. setting seeb also eliminates the requirement for the eeprom write time, t wr . because changes made with seeb enabled do not affect the eeprom, these changes are not retained through power cycles. the power-on value is the last value written with seeb disabled. this function can be used to limit the number of eeprom writes during calibration or to change the monitor thresholds periodical- ly during normal operation helping to reduce the number of times eeprom is written. figure 18 indicates which locations are shadowed eeprom. eeprom (256 bytes) ffh i 2 c address a0h i 2 c address a2h (default) auxiliary device main device 00h alarm- enable row (8 bytes) password entry (pwe) (4 bytes) table-select byte ffh 80h f8h mod offset lut ffh f8h table 01h eeprom (120 bytes) f7h 7fh 00h lower memory ffh 80h table 02h nonlookup table control and configuration registers 80h table 04h mod lookup table (72 bytes) c7h f8h table 05h alarm-enable row (8 bytes) ffh 80h table 06h tracking error lookup table (36 bytes) a3h 80h table 07h dac1 lut c7h 80h table 08h dac2 lut a3h note 1: if asel = 0, then the main device i 2 c slave address is a2h. if asel = 1, then the main device i 2 c slave address is determined by the value in table 02h, register 8ch. note 2: table 00h does not exist. note 3: alarm-enable row can be configured to exist at table 01h or table 05h using the mask bit in table 02h, register 89h. dac1 offset lut ffh f8h dac2 offset lut ffh f8h hbias lut ffh f8h figure 18. memory map
ds1873 sfp+ controller with analog ldd interface 28 ______________________________________________________________________________________ register descriptions the register maps show each byte/word (2 bytes) in terms of its row in the memory. the first byte in the row is locat- ed in memory at the row address (hexadecimal) in the leftmost column. each subsequent byte on the row is one/two memory locations beyond the previous byte/word? address. a total of 8 bytes are present on each row. for more information about each of these bytes see the corresponding register description. lower memory register map lower memory word 0 word 1 word 2 word 3 row (hex) row name byte 0/8 byte 1/9 byte 2/a byte 3/b byte 4/c byte 5/d byte 6/e byte 7/f 00 <1> threshold 0 temp alarm hi temp alarm lo temp warn hi temp warn lo 08 <1> threshold 1 v cc alarm hi v cc alarm lo v cc warn hi v cc warn lo 10 <1> threshold 2 mon1 alarm hi mon1 alarm lo mon1 warn hi mon1 warn lo 18 <1> threshold 3 mon2 alarm hi mon2 alarm lo mon2 warn hi mon2 warn lo 20 <1> threshold 4 mon3 alarm hi mon3 alarm lo mon3 warn hi mon3 warn lo 28 <1> threshold 5 mon4 alarm hi mon4 alarm lo mon4 warn hi mon4 warn lo 30C5f <1> eeprom ee ee ee ee ee ee ee ee 60 <2> adc values 0 temp value v cc value mon1 value mon2 value 68 <0> adc values 1 <2> mon3 value <2> mon4 value <2> reserved <0> status <3> update 70 <2> alarm/ warn alarm 3 alarm 2 alarm 1 alarm 0 warn 3 warn 2 reserved 78 <0> table select <2> reserved <2> reserved <6> pwe msw <6> pwe lsw <5> tbl sel access code <0> <1> <2> <3> <4> <5> <6> <7> <8> <9> <10> <11> read access all all all pw2 all n/a pw1 pw2 n/a pw2 all write access see each bit/byte separately pw2 n/a all and ds1873 hardware pw2 + mode bit all all pw1 pw2 pw2 n/a pw1 the access codes represent the factory default values of pw_ena and pw_enb (table 02h, registers c0h?1h). these registers also allow for custom permissions.
ds1873 sfp+ controller with analog ldd interface ______________________________________________________________________________________ 29 table 01h register map the alarm enable bytes (registers f8h?fh) can be configured to exist in table 05h instead of here at table 01h with the mask bit (table 02h, register 89h). if the row is configured to exist in table 05h, then these locations are empty in table 01h. table 01h word 0 word 1 word 2 word 3 row (hex) row name byte 0/8 byte 1/9 byte 2/a byte 3/b byte 4/c byte 5/d byte 6/e byte 7/f 80Cbf <8> eeprom ee ee ee ee ee ee ee ee c0Cf7 <8> eeprom ee ee ee ee ee ee ee ee f8 <8> alarm enable alarm en 3 alarm en 2 alarm en 1 alarm en 0 warn en 3 warn en 2 reserved reserved access code <0> <1> <2> <3> <4> <5> <6> <7> <8> <9> <10> <11> read access all all all pw2 all n/a pw1 pw2 n/a pw2 all write access see each bit/byte separately pw2 n/a all and ds1873 hardware pw2 + mode bit all all pw1 pw2 pw2 n/a pw1 the access codes represent the factory default values of pw_ena and pw_enb (table 02h, registers c0h?1h). these registers also allow for custom permissions.
ds1873 sfp+ controller with analog ldd interface 30 ______________________________________________________________________________________ table 02h register map table 02h word 0 word 1 word 2 word 3 row (hex) row name byte 0/8 byte 1/9 byte 2/a byte 3/b byte 4/c byte 5/d byte 6/e byte 7/f 80 <0> config 0 <8> mode <4> tindex <4> mod dac <4> dac1 value <4> dac2 value 88 <8> config 1 update rate cnfga cnfgb cnfgc device address rshift 2 rshift 1 rshift 0 90 <8> scale 0 xover coarse v cc scale mon1 scale mon2 scale 98 <8> scale 1 mon3 fine scale mon4 scale mon3 coarse scale reserved a0 <8> offset 0 xover fine v cc offset mon1 offset mon2 offset a8 <8> offset 1 mon3 fine offset mon4 offset mon3 coarse offset internal temp offset* b0 <9> pwd value pw1 msw pw1 lsw pw2 msw pw2 lsw b8 <8> threshold los ranging comp ranging ibiasmax istep htxp ltxp hlos llos c0 <8> pwd enable pw_ena pw_enb reserved reserved reserved reserved polarity tblselpon c8 <0> bias <4> man bias <4> man_ cntl <10> bias dac reserved <10> device id <10> device ver d0 <0> apc <4> apc dac <8> hbias dac reserved reserved reserved reserved reserved reserved d8Cff empty empty empty empty empty empty empty empty empty access code <0> <1> <2> <3> <4> <5> <6> <7> <8> <9> <10> <11> read access all all all pw2 all n/a pw1 pw2 n/a pw2 all write access see each bit/byte separately pw2 n/a all and ds1873 hardware pw2 + mode bit all all pw1 pw2 pw2 n/a pw1 * the final result must be xored with bb40h before writing to this register. the access codes represent the factory default values of pw_ena and pw_enb (table 02h, registers c0h?1h). these registers also allow for custom permissions.
ds1873 sfp+ controller with analog ldd interface ______________________________________________________________________________________ 31 table 04h register map table 04h (modulation lut) word 0 word 1 word 2 word 3 row (hex) row name byte 0/8 byte 1/9 byte 2/a byte 3/b byte 4/c byte 5/d byte 6/e byte 7/f 80 <8> lut4 mod mod mod mod mod mod mod mod 88 <8> lut4 mod mod mod mod mod mod mod mod 90 <8> lut4 mod mod mod mod mod mod mod mod 98 <8> lut4 mod mod mod mod mod mod mod mod a0 <8> lut4 mod mod mod mod mod mod mod mod a8 <8> lut4 mod mod mod mod mod mod mod mod b0 <8> lut4 mod mod mod mod mod mod mod mod b8 <8> lut4 mod mod mod mod mod mod mod mod c0 <8> lut4 mod mod mod mod mod mod mod mod c8Cf7 empty empty empty empty empty empty empty empty empty f8 <8> mod offset mod off mod off mod off mod off mod off mod off mod off mod off access code <0> <1> <2> <3> <4> <5> <6> <7> <8> <9> <10> <11> read access all all all pw2 all n/a pw1 pw2 n/a pw2 all write access see each bit/byte separately pw2 n/a all and ds1873 hardware pw2 + mode bit all all pw1 pw2 pw2 n/a pw1 table 05h register map table 05h is empty by default. it can be configured to contain the alarm and warning-enable bytes from table 01h, registers f8h?fh with the mask bit enabled (table 02h, register 89h). in this case table 01h is empty. table 05h word 0 word 1 word 2 word 3 row (hex) row name byte 0/8 byte 1/9 byte 2/a byte 3/b byte 4/c byte 5/d byte 6/e byte 7/f 80Cf7 empty empty empty empty empty empty empty empty empty f8 <8> alarm enable alarm en 3 alarm en 2 alarm en 1 alarm en 0 warn en 3 warn en 2 reserved reserved the access codes represent the factory default values of pw_ena and pw_enb (table 02h, registers c0h?1h). these registers also allow for custom permissions.
ds1873 sfp+ controller with analog ldd interface 32 ______________________________________________________________________________________ table 07h (dac1 lut) word 0 word 1 word 2 word 3 row (hex) row name byte 0/8 byte 1/9 byte 2/a byte 3/b byte 4/c byte 5/d byte 6/e byte 7/f 80 <8> lut7 dac1 dac1 dac1 dac1 dac1 dac1 dac1 dac1 88 <8> lut7 dac1 dac1 dac1 dac1 dac1 dac1 dac1 dac1 90 <8> lut7 dac1 dac1 dac1 dac1 dac1 dac1 dac1 dac1 98 <8> lut7 dac1 dac1 dac1 dac1 dac1 dac1 dac1 dac1 a0 <8> lut7 dac1 dac1 dac1 dac1 dac1 dac1 dac1 dac1 a8 <8> lut7 dac1 dac1 dac1 dac1 dac1 dac1 dac1 dac1 b0 <8> lut7 dac1 dac1 dac1 dac1 dac1 dac1 dac1 dac1 b8 <8> lut7 dac1 dac1 dac1 dac1 dac1 dac1 dac1 dac1 c0 <8> lut7 dac1 dac1 dac1 dac1 dac1 dac1 dac1 dac1 c8Cf7 empty empty empty empty empty empty empty empty empty f8 <8> dac1 offset dac1 off dac1 off dac1 off dac1 off dac1 off dac1 off dac1 off dac1 off access code <0> <1> <2> <3> <4> <5> <6> <7> <8> <9> <10> <11> read access all all all pw2 all n/a pw1 pw2 n/a pw2 all write access see each bit/byte separately pw2 n/a all and ds1873 hardware pw2 + mode bit all all pw1 pw2 pw2 n/a pw1 table 07h register map table 06h register map table 06h (apc lut) word 0 word 1 word 2 word 3 row (hex) row name byte 0/8 byte 1/9 byte 2/a byte 3/b byte 4/c byte 5/d byte 6/e byte 7/f 80C9f <8> lut6 apc ref apc ref apc ref apc ref apc ref apc ref apc ref apc ref 88 <8> lut6 apc ref apc ref apc ref apc ref apc ref apc ref apc ref apc ref 90 <8> lut6 apc ref apc ref apc ref apc ref apc ref apc ref apc ref apc ref 98 <8> lut6 apc ref apc ref apc ref apc ref apc ref apc ref apc ref apc ref a0 <8> lut6 apc ref apc ref apc ref apc ref reserved reserved reserved reserved a8Cf7 empty empty empty empty empty empty empty empty empty f8 <8> hbath hbias hbias hbias hbias hbias hbias hbias hbias the access codes represent the factory default values of pw_ena and pw_enb (table 02h, registers c0h?1h). these registers also allow for custom permissions.
ds1873 sfp+ controller with analog ldd interface ______________________________________________________________________________________ 33 table 08h register map access code <0> <1> <2> <3> <4> <5> <6> <7> <8> <9> <10> <11> read access all all all pw2 all n/a pw1 pw2 n/a pw2 all write access see each bit/byte separately pw2 n/a all and ds1873 hardware pw2 + mode bit all all pw1 pw2 pw2 n/a pw1 table 08h (dac2 lut) word 0 word 1 word 2 word 3 row (hex) row name byte 0/8 byte 1/9 byte 2/a byte 3/b byte 4/c byte 5/d byte 6/e byte 7/f 80 <8> lut8 dac2 dac2 dac2 dac2 dac2 dac2 dac2 dac2 88 <8> lut8 dac2 dac2 dac2 dac2 dac2 dac2 dac2 dac2 90 <8> lut8 dac2 dac2 dac2 dac2 dac2 dac2 dac2 dac2 98 <8> lut8 dac2 dac2 dac2 dac2 dac2 dac2 dac2 dac2 a0 <8> lut8 dac2 dac2 dac2 dac2 reserved reserved reserved reserved c8Cf7 empty empty empty empty empty empty empty empty empty f8 <8> dac2 offset dac2 off dac2 off dac2 off dac2 off dac2 off dac2 off dac2 off dac2 off auxiliary a0h memory register map auxiliary memory (a0h) word 0 word 1 word 2 word 3 row (hex) row name byte 0/8 byte 1/9 byte 2/a byte 3/b byte 4/c byte 5/d byte 6/e byte 7/f 00C7f <5> aux ee ee ee ee ee ee ee ee ee 80Cff <5> aux ee ee ee ee ee ee ee ee ee the access codes represent the factory default values of pw_ena and pw_enb (table 02h, registers c0h?1h). these registers also allow for custom permissions.
ds1873 sfp+ controller with analog ldd interface 34 ______________________________________________________________________________________ lower memory register descriptions lower memory, register 00h?1h: temp alarm hi lower memory, register 04h?5h: temp warn hi factory default 7fffh read access all write access pw2 or (pw1 and wlower) memory type nonvolatile (see) 00h, 04h s 2 6 2 5 2 4 2 3 2 2 2 1 2 0 01h, 05h 2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 2 -8 bit 7 bit 0 temperature measurement updates above this twos complement threshold set corresponding alarm or warning bits. temperature measurement updates equal to or below this threshold clear alarm or warning bits. lower memory, register 02h?3h: temp alarm lo lower memory, register 06h?7h: temp warn lo factory default 8000h read access all write access pw2 or (pw1 and wlower) memory type nonvolatile (see) 02h, 06h s 2 6 2 5 2 4 2 3 2 2 2 1 2 0 03h, 07h 2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 2 -8 bit 7 bit 0 temperature measurement updates below this twos complement threshold set corresponding alarm or warning bits. temperature measurement updates equal to or above this threshold clear alarm or warning bits.
ds1873 sfp+ controller with analog ldd interface ______________________________________________________________________________________ 35 lower memory, register 08h?9h: v cc alarm hi lower memory, register 0ch?dh: v cc warn hi lower memory, register 10h?1h: mon1 alarm hi lower memory, register 14h?5h: mon1 warn hi lower memory, register 18h?9h: mon2 alarm hi lower memory, register 1ch?dh: mon2 warn hi lower memory, register 20h?1h: mon3 alarm hi lower memory, register 24h?5h: mon3 warn hi lower memory, register 28h?9h: mon4 alarm hi lower memory, register 2ch?dh: mon4 warn hi factory default ffffh read access all write access pw2 or (pw1 and wlower) memory type nonvolatile (see) 08h, 0ch, 10h, 14h, 18h, 1ch, 20h, 24h, 28h, 2ch 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 09h, 0dh, 11h, 15h, 19h, 1dh, 21h, 25h, 29h, 2dh 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 voltage measurement updates above this unsigned threshold set corresponding alarm or warning bits. voltage measurements equal to or below this threshold clear alarm or warning bits.
ds1873 sfp+ controller with analog ldd interface 36 ______________________________________________________________________________________ lower memory, register 0ah?bh: v cc alarm lo lower memory, register 0eh?fh: v cc warn lo lower memory, register 12h?3h: mon1 alarm lo lower memory, register 16h?7h: mon1 warn lo lower memory, register 1ah?bh: mon2 alarm lo lower memory, register 1eh?fh: mon2 warn lo lower memory, register 22h?3h: mon3 alarm lo lower memory, register 26h?7h: mon3 warn lo lower memory, register 2ah?bh: mon4 alarm lo lower memory, register 2eh?fh: mon4 warn lo factory default 0000h read access all write access pw2 or (pw1 and wlower) memory type nonvolatile (see) 0ah, 0eh, 12h, 16h, 1ah, 1eh, 22h, 26h, 2ah, 2eh 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 0bh, 0fh, 13h, 17h, 1bh, 1fh, 23h, 27h, 2bh, 2fh 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 voltage measurement updates below this unsigned threshold set corresponding alarm or warning bits. voltage measurements equal to or above this threshold clear alarm or warning bits.
ds1873 sfp+ controller with analog ldd interface ______________________________________________________________________________________ 37 lower memory, register 30h?fh: ee factory default 00h read access all write access pw2 or (pw1 and wlower) memory type nonvolatile (ee) 30hC5fh ee ee ee ee ee ee ee ee bit 7 bit 0 pw2 level access-controlled eeprom. power-on value 0000h read access all write access n/a memory type volatile 60h s 2 6 2 5 2 4 2 3 2 2 2 1 2 0 61h 2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 2 -8 bit 7 bit 0 signed twos complement direct-to-temperature measurement. lower memory, register 60h?1h: temp value
ds1873 sfp+ controller with analog ldd interface 38 ______________________________________________________________________________________ lower memory, register 6ch?dh: reserved power-on value 00h read access all write access n/a memory type 6ch, 6dh 0 0 0 0 0 0 0 0 bit 7 bit 0 these registers are reserved. the value when read is 00h. power-on value 0000h read access all write access n/a memory type volatile 62h, 64h, 66h, 68h, 6ah 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 63h, 65h, 67h, 69h, 6bh 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 left-justified unsigned voltage measurement. lower memory, register 62h?3h: v cc value lower memory, register 64h?5h: mon1 value lower memory, register 66h?7h: mon2 value lower memory, register 68h?9h: mon3 value lower memory, register 6ah?bh: mon4 value
ds1873 sfp+ controller with analog ldd interface ______________________________________________________________________________________ 39 power-on value x0xx 0xxxb read access all write access see below memory type volatile write access n/a all n/a all all n/a n/a n/a 6eh txds txdc in1s rsels rselc txfs rxl rdyb bit 7 bit 0 bit 7 txds: txd status bit. reflects the logic state of the txd pin (read only). 0 = txd pin is logic-low. 1 = txd pin is logic-high. bit 6 txdc: txd software control bit. this bit allows for software control that is identical to the txd pin. see the section on txd for further information. its value is wire-ored with the logic value of the txd pin (writable by all users). 0 = (default). 1 = forces the device into a txd state regardless of the value of the txd pin. bit 5 in1s: in1 status bit. reflects the logic state of the in1 pin (read only). 0 = in1 pin is logic-low. 1 = in1 pin is logic-high. bit 4 rsels: rsel status bit. reflects the logic state of the rsel pin (read only). 0 = rsel pin is logic-low. 1 = rsel pin is logic-high. bit 3 rselc: rsel software control bit. this bit allows for software control that is identical to the rsel pin. its value is wire-ored with the logic value of the rsel pin to create the rselout pins logic value (writable by all users). 0 = (default). 1 = forces the device into a rsel state regardless of the value of the rsel pin. bit 2 txfs: reflects the driven state of the txf pin (read only). 0 = txf pin is low. 1 = txf pin is high. bit 1 rxl: reflects the driven state of the losout pin (read only). 0 = losout pin is driven low. 1 = losout pin is pulled high. bit 0 rdyb: ready bar. 0 = v cc is above poa. 1 = v cc is below poa and/or too low to communicate over the i 2 c bus. lower memory, register 6eh: status
ds1873 sfp+ controller with analog ldd interface 40 ______________________________________________________________________________________ lower memory, register 6fh: update power-on value 00h read access all write access all and ds 1873 hardware memory type volatile 6fh temp rdy vcc rdy mon1 rdy mon2 rdy mon3 rdy mon4 rdy reserved rssir bit 7 bit 0 bits 7:2 update of completed conversions. at power-on, these bits are cleared and are set as each conversion is completed. these bits can be cleared so that a completion of a new conversion is verified. bit 1 reserved bit 0 rssir: rssi range. reports the range used for conversion update of mon3. 0 = fine range is the reported value. 1 = coarse range is the reported value.
ds1873 sfp+ controller with analog ldd interface ______________________________________________________________________________________ 41 power-on value 10h read access all write access n/a memory type volatile 70h temp hi temp lo vcc hi vcc lo mon1 hi mon1 lo mon2 hi mon2 lo bit 7 bit 0 bit 7 temp hi: high-alarm status for temperature measurement. 0 = (default) last measurement was equal to or below threshold setting. 1 = last measurement was above threshold setting. bit 6 temp lo: low-alarm status for temperature measurement. 0 = (default) last measurement was equal to or above threshold setting. 1 = last measurement was below threshold setting. bit 5 vcc hi: high-alarm status for v cc measurement. 0 = (default) last measurement was equal to or below threshold setting. 1 = last measurement was above threshold setting. bit 4 vcc lo: low-alarm status for v cc measurement. this bit is set when the v cc supply is below the poa trip point value. it clears itself when a v cc measurement is completed and the value is above the low threshold. 0 = last measurement was equal to or above threshold setting. 1 = (default) last measurement was below threshold setting. bit 3 mon1 hi: high-alarm status for mon1 measurement. 0 = (default) last measurement was equal to or below threshold setting. 1 = last measurement was above threshold setting. bit 2 mon1 lo: low-alarm status for mon1 measurement. 0 = (default) last measurement was equal to or above threshold setting. 1 = last measurement was below threshold setting. bit 1 mon2 hi: high-alarm status for mon2 measurement. 0 = (default) last measurement was equal to or below threshold setting. 1 = last measurement was above threshold setting. bit 0 mon2 lo: low-alarm status for mon2 measurement. 0 = (default) last measurement was equal to or above threshold setting. 1 = last measurement was below threshold setting. lower memory, register 70h: alarm 3
ds1873 sfp+ controller with analog ldd interface 42 ______________________________________________________________________________________ lower memory, register 71h: alarm 2 power-on value 00h read access all write access n/a memory type volatile 71h mon3 hi mon3 lo mon4 hi mon4 lo reserved reserved reserved txfint bit 7 bit 0 bit 7 mon3 hi: high-alarm status for mon3 measurement. a txd event does not clear this alarm. 0 = (default) last measurement was equal to or below threshold setting. 1 = last measurement was above threshold setting. bit 6 mon3 lo: low-alarm status for mon3 measurement. a txd event does not clear this alarm. 0 = (default) last measurement was equal to or above threshold setting. 1 = last measurement was below threshold setting. bit 5 mon4 hi: high-alarm status for mon4 measurement. a txd event does not clear this alarm. 0 = (default) last measurement was equal to or below threshold setting. 1 = last measurement was above threshold setting. bit 4 mon4 lo: low-alarm status for mon4 measurement. a txd event does not clear this alarm. 0 = (default) last measurement was equal to or above threshold setting. 1 = last measurement was below threshold setting. bits 3:1 reserved bit 0 txfint: txf interrupt. this bit is the wire-ored logic of all alarms and warnings wire-anded with their corresponding enable bits in addition to nonmaskable alarms txp hi, txp lo, bias max, and hbal. the enable bits are found in table 01h/05h, registers f8hCffh.
ds1873 sfp+ controller with analog ldd interface ______________________________________________________________________________________ 43 lower memory, register 72h: alarm 1 power-on value 00h read access all write access n/a memory type volatile 72h reserved reserved reserved reserved hbal reserved txp hi txp lo bit 7 bit 0 bits 7:4 reserved bit 3 hbal: high-bias alarm status; fast comparison. a txd event clears this alarm. 0 = (default) last comparison was below threshold setting. 1 = last comparison was above threshold setting. bit 2 reserved bit 1 txp hi: high-alarm status txp; fast comparison. a txd event clears this alarm. 0 = (default) last comparison was below threshold setting. 1 = last comparison was above threshold setting. bit 0 txp lo: low-alarm status txp; fast comparison. a txd event clears this alarm. 0 = (default) last comparison was above threshold setting. 1 = last comparison was below threshold setting. power-on value 00h read access all write access n/a memory type volatile 73h los hi los lo reserved reserved bias max reserved reserved reserved bit 7 bit 0 bit 7 los hi: high-alarm status for mon3; fast comparison. a txd event does not clear this alarm. 0 = (default) last comparison was below threshold setting. 1 = last comparison was above threshold setting. bit 6 los lo: low-alarm status for mon3; fast comparison. a txd event does not clear this alarm. 0 = (default) last comparison was above threshold setting. 1 = last comparison was below threshold setting. bits 5:4 reserved bit 3 bias max: alarm status for maximum digital setting of bias. a txd event clears this alarm. 0 = (default) the value for bias is equal to or below the ibiasmax register. 1 = requested value for bias is greater than the ibiasmax register. bits 2:0 reserved lower memory, register 73h: alarm 0
ds1873 sfp+ controller with analog ldd interface 44 ______________________________________________________________________________________ lower memory, register 74h: warn 3 power-on value 10h read access all write access n/a memory type volatile 74h temp hi temp lo vcc hi vcc lo mon1 hi mon1 lo mon2 hi mon2 lo bit 7 bit 0 bit 7 temp hi: high-warning status for temperature measurement. 0 = (default) last measurement was equal to or below threshold setting. 1 = last measurement was above threshold setting. bit 6 temp lo: low-warning status for temperature measurement. 0 = (default) last measurement was equal to or above threshold setting. 1 = last measurement was below threshold setting. bit 5 vcc hi: high-warning status for v cc measurement. 0 = (default) last measurement was equal to or below threshold setting. 1 = last measurement was above threshold setting. bit 4 vcc lo: low-warning status for v cc measurement. this bit is set when the v cc supply is below the poa trip point value. it clears itself when a v cc measurement is completed and the value is above the low threshold. 0 = last measurement was equal to or above threshold setting. 1 = (default) last measurement was below threshold setting. bit 3 mon1 hi: high-warning status for mon1 measurement. 0 = (default) last measurement was equal to or below threshold setting. 1 = last measurement was above threshold setting. bit 2 mon1 lo: low-warning status for mon1 measurement. 0 = (default) last measurement was equal to or above threshold setting. 1 = last measurement was below threshold setting. bit 1 mon2 hi: high-warning status for mon2 measurement. 0 = (default) last measurement was equal to or below threshold setting. 1 = last measurement was above threshold setting. bit 0 mon2 lo: low-warning status for mon2 measurement. 0 = (default) last measurement was equal to or above threshold setting. 1 = last measurement was below threshold setting.
ds1873 sfp+ controller with analog ldd interface ______________________________________________________________________________________ 45 lower memory, register 75h: warn 2 power-on value 00h read access all write access n/a memory type volatile 75h mon3 hi mon3 lo mon4 hi mon4 lo reserved reserved reserved reserved bit 7 bit 0 bit 7 mon3 hi: high-warning status for mon3 measurement. 0 = (default) last measurement was equal to or below threshold setting. 1 = last measurement was above threshold setting. bit 6 mon3 lo: low-warning status for mon3 measurement. 0 = (default) last measurement was equal to or above threshold setting. 1 = last measurement was below threshold setting. bit 5 mon4 hi: high-warning status for mon4 measurement. 0 = (default) last measurement was equal to or below threshold setting. 1 = last measurement was above threshold setting. bit 4 mon4 lo: low-warning status for mon4 measurement. 0 = (default) last measurement was equal to or above threshold setting. 1 = last measurement was below threshold setting. bits 3:0 reserved power-on value 00h read access all write access n/a memory type these registers are reserved. the value when read is 00h. lower memory, register 76h?ah: reserved
ds1873 sfp+ controller with analog ldd interface 46 ______________________________________________________________________________________ lower memory, register 7bh?eh: password entry (pwe) power-on value ffff ffffh read access n/a write access all memory type volatile 7bh 2 31 2 30 2 29 2 28 2 27 2 26 2 25 2 24 7ch 2 23 2 22 2 21 2 20 2 19 2 18 2 17 2 16 7dh 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 7eh 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 there are two passwords for the ds1873. each password is 4 bytes long. the lower level password (pw1) has all the access of a normal user plus those made available with pw1. the higher level password (pw2) has all the access of pw1 plus those made available with pw2. the values of the passwords reside in eeprom inside pw2 memory. at power-up, all pwe bits are set to 1. all reads at this location are 0. power-on value tblselpon (table 02h, register c7h) read access all write access all memory type volatile 7fh 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 the upper memory tables of the ds1873 are accessible by writing the desired table value in this register. the power-on value of this register is defined by the value written to tblselpon (table 02h, register c7h). lower memory, register 7fh: table select (tbl sel)
ds1873 sfp+ controller with analog ldd interface ______________________________________________________________________________________ 47 table 01h register descriptions table 01h, register 80h?fh: eeprom power-on value 00h read access pw2 or (pw1 and rwtbl1a) or (pw1 and rtbl1a) write access pw2 or (pw1 and rwtbl1a) memory type nonvolatile (ee) 80hCbfh ee ee ee ee ee ee ee ee bit 7 bit 0 eeprom for pw1 and/or pw2 level access. power-on value 00h read access pw2 or (pw1 and rwtbl1b) or (pw1 and rtbl1b) write access pw2 or (pw1 and rwtbl1b) memory type nonvolatile (ee) c0hCf7h ee ee ee ee ee ee ee ee bit 7 bit 0 eeprom for pw1 and/or pw2 level access. table 01h, register c0h?7h: eeprom
ds1873 sfp+ controller with analog ldd interface 48 ______________________________________________________________________________________ table 01h, register f8h: alarm en 3 power-on value 00h read access pw2 or (pw1 and rwtbl1c) or (pw1 and rtbl1c) write access pw2 or (pw1 and rwtbl1c) memory type nonvolatile (see) f8h temp hi temp lo vcc hi vcc lo mon1 hi mon1 lo mon2 hi mon2 lo bit 7 bit 0 layout is identical to alarm 3 in lower memory, register 70h. enables alarms to create txfint (lower memory, register 71h) logic. the mask bit (table 02h, register 89h) determines whether this memory exists in table 01h or 05h. bit 7 temp hi: 0 = disables interrupt from temp hi alarm. 1 = enables interrupt from temp hi alarm. bit 6 temp lo: 0 = disables interrupt from temp lo alarm. 1 = enables interrupt from temp lo alarm. bit 5 vcc hi: 0 = disables interrupt from vcc hi alarm. 1 = enables interrupt from vcc hi alarm. bit 4 vcc lo: 0 = disables interrupt from vcc lo alarm. 1 = enables interrupt from vcc lo alarm. bit 3 mon1 hi: 0 = disables interrupt from mon1 hi alarm. 1 = enables interrupt from mon1 hi alarm. bit 2 mon1 lo: 0 = disables interrupt from mon1 lo alarm. 1 = enables interrupt from mon1 lo alarm. bit 1 mon2 hi: 0 = disables interrupt from mon2 hi alarm. 1 = enables interrupt from mon2 hi alarm. bit 0 mon2 lo: 0 = disables interrupt from mon2 lo alarm. 1 = enables interrupt from mon2 lo alarm.
ds1873 sfp+ controller with analog ldd interface ______________________________________________________________________________________ 49 table 01h, register f9h: alarm en 2 power-on value 00h read access pw2 or (pw1 and rwtbl1c) or (pw1 and rtbl1c) write access pw2 or (pw1 and rwtbl1c) memory type nonvolatile (see) f9h mon3 hi mon3 lo mon4 hi mon4 lo reserved reserved reserved reserved bit 7 bit 0 layout is identical to alarm 2 in lower memory, register 71h. enables alarms to create txfint (lower memory, register 71h) logic. the mask bit (table 02h, register 89h) determines whether this memory exists in table 01h or 05h. bit 7 mon3 hi: 0 = disables interrupt from mon3 hi alarm. 1 = enables interrupt from mon3 hi alarm. bit 6 mon3 lo: 0 = disables interrupt from mon3 lo alarm. 1 = enables interrupt from mon3 lo alarm. bit 5 mon4 hi: 0 = disables interrupt from mon4 hi alarm. 1 = enables interrupt from mon4 hi alarm. bit 4 mon4 lo: 0 = disables interrupt from mon4 lo alarm. 1 = enables interrupt from mon4 lo alarm. bit 3:0 reserved
ds1873 sfp+ controller with analog ldd interface 50 ______________________________________________________________________________________ table 01h, register fah: alarm en 1 power-on value 00h read access pw2 or (pw1 and rwtbl1c) or (pw1 and rtbl1c) write access pw2 or (pw1 and rwtbl1c) memory type nonvolatile (see) fah reserved reserved reserved reserved hbal reserved txp hi txp lo bit 7 bit 0 layout is identical to alarm 1 in lower memory, register 72h. enables alarms to create internal signal fetg (see figure 13) logic. the mask bit (table 02h, register 89h) determines whether this memory exists in table 01h or 05h. bits 7:4 reserved bit 3 hbal: 0 = disables interrupt from hbal alarm. 1 = enables interrupt from hbal alarm. bit 2 reserved bit 1 txp hi: 0 = disables interrupt from txp hi alarm. 1 = enables interrupt from txp hi alarm. bit 0 txp lo: 0 = disables interrupt from txp lo alarm. 1 = enables interrupt from txp lo alarm.
ds1873 sfp+ controller with analog ldd interface ______________________________________________________________________________________ 51 table 01h, register fbh: alarm en 0 power-on value 00h read access pw2 or (pw1 and rwtbl1c) or (pw1 and rtbl1c) write access pw2 or (pw1 and rwtbl1c) memory type nonvolatile (see) fbh los hi los lo reserved reserved bias max reserved reserved reserved bit 7 bit 0 layout is identical to alarm 0 in lower memory, register 73h. the mask bit (table 02h, register 89h) determines whether this memory exists in table 01h or 05h. bit 7 los hi: enables alarm to create txfint (lower memory, register 71h) logic. 0 = disables interrupt from los hi alarm. 1 = enables interrupt from los hi alarm. bit 6 los lo: enables alarm to create txfint (lower memory, register 71h) logic. 0 = disables interrupt from los lo alarm. 1 = enables interrupt from los lo alarm. bits 5:4 reserved bit 3 bias max: enables alarm to create internal signal fetg (see figure 13) logic. 0 = disables interrupt from bias max alarm. 1 = enables interrupt from bias max alarm. bits 2:0 reserved
ds1873 sfp+ controller with analog ldd interface 52 ______________________________________________________________________________________ table 01h, register fch: warn en 3 power-on value 00h read access pw2 or (pw1 and rwtbl1c) or (pw1 and rtbl1c) write access pw2 or (pw1 and rwtbl1c) memory type nonvolatile (see) fch temp hi temp lo vcc hi vcc lo mon1 hi mon1 lo mon2 hi mon2 lo bit 7 bit 0 layout is identical to warn 3 in lower memory, register 74h. enables warnings to create txfint (lower memory, register 71h) logic. the mask bit (table 02h, register 89h) determines whether this memory exists in table 01h or 05h. bit 7 temp hi: 0 = disables interrupt from temp hi warning. 1 = enables interrupt from temp hi warning. bit 6 temp lo: 0 = disables interrupt from temp lo warning. 1 = enables interrupt from temp lo warning. bit 5 vcc hi: 0 = disables interrupt from vcc hi warning. 1 = enables interrupt from vcc hi warning. bit 4 vcc lo: 0 = disables interrupt from vcc lo warning. 1 = enables interrupt from vcc lo warning. bit 3 mon1 hi: 0 = disables interrupt from mon1 hi warning. 1 = enables interrupt from mon1 hi warning. bit 2 mon1 lo: 0 = disables interrupt from mon1 lo warning. 1 = enables interrupt from mon1 lo warning. bit 1 mon2 hi: 0 = disables interrupt from mon2 hi warning. 1 = enables interrupt from mon2 hi warning. bit 0 mon2 lo: 0 = disables interrupt from mon2 lo warning. 1 = enables interrupt from mon2 lo warning.
ds1873 sfp+ controller with analog ldd interface ______________________________________________________________________________________ 53 table 01h, register fdh: warn en 2 power-on value 00h read access pw2 or (pw1 and rwtbl1c) or (pw1 and rtbl1c) write access pw2 or (pw1 and rwtbl1c) memory type nonvolatile (see) fdh mon3 hi mon3 lo mon4 hi mon4 lo reserved reserved reserved reserved bit 7 bit 0 layout is identical to warn 2 in lower memory, register 75h. enables warnings to create txfint (lower memory, register 71h) logic. the mask bit (table 02h, register 89h) determines whether this memory exists in table 01h or 05h. bit 7 mon3 hi: 0 = disables interrupt from mon3 hi warning. 1 = enables interrupt from mon3 hi warning. bit 6 mon3 lo: 0 = disables interrupt from mon3 lo warning. 1 = enables interrupt from mon3 lo warning. bit 5 mon4 hi: 0 = disables interrupt from mon4 hi warning. 1 = enables interrupt from mon4 hi warning. bit 4 mon4 lo: 0 = disables interrupt from mon4 lo warning. 1 = enables interrupt from mon4 lo warning. bits 3:0 reserved power-on value 00h read access pw2 or (pw1 and rwtbl1c) or (pw1 and rtbl1c) write access pw2 or (pw1 and rwtbl1c) memory type nonvolatile (see) these registers are reserved. table 01h, register feh?fh: reserved
ds1873 sfp+ controller with analog ldd interface 54 ______________________________________________________________________________________ table 02h register descriptions table 02h, register 80h: mode power-on value 3fh read access pw2 or (pw1 and rwtbl2) or (pw1 and rtbl2) write access pw2 or (pw1 and prtbl2) memory type volatile 80h seeb reserved dac1 en dac2 en aen mod en apc en bias en bit 7 bit 0 bit 7 seeb: 0 = (default) enables eeprom writes to see bytes. 1 = disables eeprom writes to see bytes during configuration, so that the configuration of the part is not delayed by the ee cycle time. once the values are known, write this bit to a 0 and write the see locations again for data to be written to the eeprom. bit 6 reserved bit 5 dac1 en: 0 = dac1 value is writable by the user and the lut recalls are disabled. this allows users to interactively test their modules by writing the values for dac1. the output is updated with the new value at the end of the write cycle. the i 2 c stop condition is the end of the write cycle. 1 = (default) enables auto control of the lut for dac1 value. bit 4 dac2 en: 0 = dac2 value is writable by the user and the lut recalls are disabled. this allows users to interactively test their modules by writing the values for dac2. the output is updated with the new value at the end of the write cycle. the i 2 c stop condition is the end of the write cycle. 1 = (default) enables auto control of the lut for dac2 value. bit 3 aen: 0 = the temperature-calculated index value tindex is writable by users and the updates of calculated indexes are disabled. this allows users to interactively test their modules by controlling the indexing for the luts. the recalled values from the luts appear in the dac registers after the next completion of a temperature conversion. bit 2 mod en: 0 = modulation is writable by the user and the lut recalls are disabled. this allows users to interactively test their modules by writing the dac value for modulation. the output is updated with the new value at the end of the write cycle. the i 2 c stop condition is the end of the write cycle. 1 = (default) enables auto control of the lut for modulation. bit 1 apc en: 0 = apc dac is writable by the user and the lut recalls are disabled. this allows users to interactively test their modules by writing the dac value for apc reference. the i 2 c stop condition is the end of the write cycle. the hbias dac is also writable if recalls are disabled. 1 = (default) enables auto control of the lut for apc reference. bit 0 bias en: 0 = bias dac is controlled by the user and the apc is in manual mode. this allows the user to interactively test their modules by writing the dac value for bias. 1 = (default) enables auto control for the apc feedback.
ds1873 sfp+ controller with analog ldd interface ______________________________________________________________________________________ 55 table 02h, register 81h: temperature index (tindex) factory default 00h read access pw2 or (pw1 and rwtbl2) or (pw1 and rtbl2) write access (pw2 and aen = 0) or (pw1 and rwtbl2 and aen = 0) memory type volatile 81h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 holds the calculated index based on the temperature measurement. this index is used for the address during lookup of tables 04h, 06hC08h. temperature measurements below -40c or above +102c are clamped to 80h and c7h, respectively. the calculation of tindex is as follows: tindex = temp _ value + 40 c 2 c + 80h for the temperature-indexed luts (2c and 4c), the index used during the lookup function for each table is as follows: table 04h (mod) 1 tindex 6 tindex 5 tindex 4 tindex 3 tindex 2 tindex 1 tindex 0 table 06h (apc) 1 0 tindex 6 tindex 5 tindex 4 tindex 3 tindex 2 tindex 1 table 07h (dac1) 1 tindex 6 tindex 5 tindex 4 tindex 3 tindex 2 tindex 1 tindex 0 table 08h (dac2) 1 0 tindex 6 tindex 5 tindex 4 tindex 3 tindex 2 tindex 1 for the 8-position lut tables, the following table shows the lookup function: tindex 1000_0xxx 1001_0xxx 1001_1xxx 1010_0xxx 1010_1xxx 1011_0xxx 1011_1xxx 11xx_xxxx byte f8 f9 fa fb fc fd fe ff temp (c) < -8 -8 to +8 8 to 24 24 to 40 40 to 56 56 to 72 72 to 88 88
ds1873 sfp+ controller with analog ldd interface 56 ______________________________________________________________________________________ table 02h, register 84h?5h: dac1 value factory default 0000h read access pw2 or (pw1 and rwtbl246) or (pw1 and rtbl246) write access (pw2 and dac1 en = 0) or (pw1 and rwtbl246 and dac1 en = 0) memory type volatile 84h 0 0 0 0 0 0 0 2 8 85h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 the digital value used for dac1. it is the result of lut7 plus dac1 offset times 4 recalled from table 07h at the adjusted memory address found in tindex. this register is updated at the end of the temperature conversion. dac1 value = lut7 + dac1 offset 4 v dac1 = v refin 1024 dac1 value factory default 0000h read access pw2 or (pw1 and rwtbl2) or (pw1 and rtbl2) write access (pw2 and mod en = 0) or (pw1 and rwtbl2 and mod en = 0) memory type volatile 82h 0 0 0 0 0 0 0 2 8 83h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 the digital value used for mod dac. it is the result of lut4 plus mod offset times 4 recalled from table 04h at the adjusted memory address found in tindex. this register is updated at the end of the temperature conversion. mod value = lut4 + mod offset 4 v mod = v refin 1024 mod value table 02h, register 82h?3h: mod dac
ds1873 sfp+ controller with analog ldd interface ______________________________________________________________________________________ 57 table 02h, register 88h: update rate factory default 00h read access pw2 or (pw1 and rwtbl2) or (pw1 and rtbl2) write access pw2 or (pw1 and rwtbl2) memory type nonvolatile (see) 88h see see see see apc_sr 3 apc_sr 2 apc_sr 1 apc_sr 0 bit 7 bit 0 bits 7:4 see bits 3:0 apc_sr[3:0]: 4-bit sample rate for comparison of apc control. defines the sample rate for comparison of apc control. the quick-trip comparator uses a 1.6s window to sample each input. after an apc comparison that requires an update to the bias dac, a settling time (as calculated below) is required to allow for the feedback on bmd (mon2) to stabilize. this time is dependent on the time constant of the filter pole used for the delta-to-sigma bias output. during the timing of the settling rate, comparisons of apc comparisons of bmd are ignored until 32 sample periods (t rep ) have passed. settlingtime = 51.2s x (apc_sr[3:0] + 1) factory default 0000h read access pw2 or (pw1 and rwtbl246) or (pw1 and rtbl246) write access (pw2 and dac2 en = 0) or (pw1 and rwtbl246 and dac2 en = 0) memory type volatile 86h 0 0 0 0 0 0 0 2 8 87h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 the digital value used for dac2. it is the result of lut8 plus dac2 offset times 4 recalled from table 08h at the adjusted memory address found in tindex. this register is updated at the end of the temperature conversion. dac2 value = lut8 + dac2 offset 4 v dac2 = v refin 1024 dac2 value table 02h, register 86h?7h: dac2 value
ds1873 sfp+ controller with analog ldd interface 58 ______________________________________________________________________________________ factory default 80h read access pw2 or (pw1 and rwtbl2) or (pw1 and rtbl2) write access pw2 or (pw1 and rwtbl2) memory type nonvolatile (see) 89h losc reserved inv los asel mask invrsout reserved reserved bit 7 bit 0 bit 7 losc: los configuration. defines the source for the losout pin (see figure 14). 0 = los lo alarm is used as the source. 1 = (default) los input pin is used as the source. bit 6 reserved bit 5 inv los: inverts the buffered input pin los to output pin losout (see figure 14). 0 = noninverted los to losout pin. 1 = inverted los to losout pin. bit 4 asel: address select. 0 = device address is a2h. 1 = byte device address in table 02h, register 8ch is used as the device address. bit 3 mask: 0 = alarm-enable row exists at table 01h, registers f8hCffh. table 05h, registers f8hCffh are empty. 1 = alarm-enable row exists at table 05h, registers f8hCffh. table 01h, registers f8hCffh are empty. bit 2 invrsout: allow for inversion of rselout pin (see figure 14). 0 = rselout is not inverted. 1 = rselout is inverted. bits 1:0 reserved table 02h, register 89h: cnfga
ds1873 sfp+ controller with analog ldd interface ______________________________________________________________________________________ 59 table 02h, register 8ah: cnfgb factory default 00h read access pw2 or (pw1 and rwtbl2) or (pw1 and rtbl2) write access pw2 or (pw1 and rwtbl2) memory type nonvolatile (see) 8ah in1c invout1 reserved reserved reserved alatch qtlatch wlatch bit 7 bit 0 bit 7 in1c: in1 software control bit (see figure 14). 0 = in1 pins logic controls out1 pin. 1 = out1 is active (bit 6 defines the polarity). bit 6 invout1: inverts the active state for out1 (see figure 14). 0 = noninverted. 1 = inverted. bits 5:3 reserved bit 2 alatch: adc alarms comparison latch. lower memory, registers 70hC71h. 0 = adc alarm flags reflect the status of the last comparison. 1 = adc alarm flags remain set. bit 1 qtlatch: quick trips comparison latch. lower memory, registers 72hC73h. 0 = qt alarm and warning flags reflect the status of the last comparison. 1 = qt alarm and warning flags remain set. bit 0 wlatch: adc warnings comparison latch. lower memory, registers 74hC75h. 0 = adc warning flags reflect the status of the last comparison. 1 = adc warning flags remain set.
ds1873 sfp+ controller with analog ldd interface 60 ______________________________________________________________________________________ table 02h, register 8bh: cnfgc factory default 00h read access pw2 or (pw1 and rwtbl2) or (pw1 and rtbl2) write access pw2 or (pw1 and rwtbl2) memory type nonvolatile (see) 8bh xoveren reserved txdm34 txdfg txdflt txdio rssi_fc rssi_ff bit 7 bit 0 bit 7 xoveren: enables rssi conversion to use the xover fine (table 02h, register a0hCa1h) value during mon3 conversions. 0 = uses hysteresis for linear rssi measurements. 1 = xover value is enabled for nonlinear rssi measurements. bit 6 reserved bit 5 txdm34: enables txd to reset alarms, warnings, and quick trips associated to mon3 and mon4 during a txd event. 0 = txd event has no effect on the mon3 and mon4 alarms, warnings, and quick trips. 1 = mon3 and mon4 alarms, warnings, and quick trips are reset during a txd event. bit 4 txdfg: see figure 13. 0 = fetg, an internal signal, has no effect on txdout. 1 = fetg is enabled and ored with other possible signals to create txdout. bit 3 txdflt: see figure 13. 0 = txf pin has no effect on txdout. 1 = txf pin is enabled and ored with other possible signals to create txdout. bit 2 txdio: see figure 13. 0 = (default) txd input signal has no effect on txdout. 1 = txd input signal is enabled and ored with other possible signals to create txdout. bits 1:0 rssi_fc and rssi_ff: rssi force coarse and rssi force fine. control bits for rssi mode of operation on the mon3 conversion. 00b = normal rssi mode of operation (default). 01b = the fine settings of scale and offset are used for mon3 conversions. 10b = the coarse settings of scale and offset are used for mon3 conversions. 11b = normal rssi mode of operation.
ds1873 sfp+ controller with analog ldd interface ______________________________________________________________________________________ 61 factory default 00h read access pw2 or (pw1 and rwtbl2) or (pw1 and rtbl2) write access pw2 or (pw1 and rwtbl2) memory type nonvolatile (see) 8ch 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 this value becomes the i 2 c slave address for the main memory when the asel (table 02h, register 89h) bit is set. if a0h is programmed to this register, the auxiliary memory is disabled. table 02h, register 8ch: device address table 02h, register 8dh: right-shift 2 (rshift 2 ) factory default 00h read access pw2 or (pw1 and rwtbl2) or (pw1 and rtbl2) write access pw2 or (pw1 and rwtbl2) memory type nonvolatile (see) 8dh reserved reserved reserved reserved reserved mon3c 2 mon3c 1 mon3c 0 bit 7 bit 0 allows for right-shifting the final answer of mon3 coarse voltage measurement. this allows for scaling the measurement to the smallest full-scale voltage and then right-shifting the final result so the reading is weighted to the correct lsb.
ds1873 sfp+ controller with analog ldd interface 62 ______________________________________________________________________________________ factory default 00h read access pw2 or (pw1 and rwtbl2) or (pw1 and rtbl2) write access pw2 or (pw1 and rwtbl2) memory type nonvolatile (see) 8eh reserved mon1 2 mon1 1 mon1 0 reserved mon2 2 mon2 1 mon2 0 bit 7 bit 0 allows for right-shifting the final answer of mon1 and mon2 voltage measurements. this allows for scaling the measurements to the smallest full-scale voltage and then right-shifting the final result so the reading is weighted to the correct lsb. factory default 30h read access pw2 or (pw1 and rwtbl2) or (pw1 and rtbl2) write access pw2 or (pw1 and rwtbl2) memory type nonvolatile (see) 8fh reserved mon3f 2 mon3f 1 mon3f 0 reserved mon4 2 mon4 1 mon4 0 bit 7 bit 0 allows for right-shifting the final answer of mon3 fine and mon4 voltage measurements. this allows for scaling the measurements to the smallest full-scale voltage and then right-shifting the final result so the reading is weighted to the correct lsb. the mon3 right-shifting is only available for the fine mode of operation. the coarse mode does not right-shift. table 02h, register 8eh: right-shift 1 (rshift 1 ) table 02h, register 8fh: right-shift 0 (rshift 0 )
ds1873 sfp+ controller with analog ldd interface ______________________________________________________________________________________ 63 table 02h, register 90h?1h: xover coarse factory default 0000h read access pw2 or (pw1 and rwtbl2) or (pw1 and rtbl2) write access pw2 or (pw1 and rwtbl2) memory type nonvolatile (see) 90h 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 91h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 0 bit 7 bit 0 defines the crossover value for rssi measurements of nonlinear inputs when xoveren is set to a 1 (table 02h, register 8bh). mon3 coarse conversion results (before right-shifting) less than this register are clamped to the value of this register. factory calibrated read access pw2 or (pw1 and rwtbl246) or (pw1 and rtbl246) write access pw2 or (pw1 and rwtbl246) memory type nonvolatile (see) 92h, 94h, 96h, 98h, 9ah, 9ch 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 93h, 95h, 97h, 99h, 9bh, 9dh 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 controls the scaling or gain of the fs voltage measurements. the factory-calibrated value produces an fs voltage of 6.5536v for v cc ; 2.5v for mon1, mon2, mon4; and 0.3125v for mon3 fine. table 02h, register 92h?3h: v cc scale table 02h, register 94h?5h: mon1 scale table 02h, register 96h?7h: mon2 scale table 02h, register 98h?9h: mon3 fine scale table 02h, register 9ah?bh: mon4 scale table 02h, register 9ch?dh: mon3 coarse scale
ds1873 sfp+ controller with analog ldd interface 64 ______________________________________________________________________________________ factory default ffffh read access pw2 or (pw1 and rwtbl2) or (pw1 and rtbl2) write access pw2 or (pw1 and rwtbl2) memory type nonvolatile (see) a0h 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 a1h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 0 bit 7 bit 0 defines the crossover value for rssi measurements of nonlinear inputs when xoveren is set to a 1 (table 02h, register 8bh). mon3 fine conversion results (before right-shifting) greater than this register require a mon3 coarse conversion. table 02h, register a0h?1h: xover fine factory default 00h read access pw2 or (pw1 and rwtbl2) or (pw1 and rtbl2) write access pw2 or (pw1 and rwtbl2) memory type nonvolatile (see) these registers are reserved. table 02h, register 9eh?fh: reserved
ds1873 sfp+ controller with analog ldd interface ______________________________________________________________________________________ 65 table 02h, register a2h?3h: v cc offset table 02h, register a4h?5h: mon1 offset table 02h, register a6h?7h: mon2 offset table 02h, register a8h?9h: mon3 fine offset table 02h, register aah?bh: mon4 offset table 02h, register ach?dh: mon3 coarse offset factory default 00h read access pw2 or (pw1 and rwtbl2) or (pw1 and rtbl2) write access pw2 or (pw1 and rwtbl2) memory type nonvolatile (see) a2h, a4h, a6h, a8h, aah, ach s s 2 15 2 14 2 13 2 12 2 11 2 10 a3h, a5h, a7h, a9h, abh, adh 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 bit 7 bit 0 allows for offset control of these voltage measurements if desired. this number is twos complement. factory calibrated read access pw2 or (pw1 and rwtbl2) or (pw1 and rtbl2) write access pw2 or (pw1 and rwtbl2) memory type nonvolatile (see) aeh s 2 8 2 7 2 6 2 5 2 4 2 3 2 2 afh 2 1 2 0 2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 bit 7 bit 0 allows for offset control of temperature measurement if desired. the final result must be xored with bb40h before writing to this register. factory calibration contains the desired value for a reading in degrees celsius. table 02h, register aeh?fh: internal temp offset
ds1873 sfp+ controller with analog ldd interface 66 ______________________________________________________________________________________ table 02h, register b0h?3h: pw1 factory default ffff ffffh read access n/a write access pw2 or (pw1 and wpw1) memory type nonvolatile (see) b0h 2 31 2 30 2 29 2 28 2 27 2 26 2 25 2 24 b1h 2 23 2 22 2 21 2 20 2 19 2 18 2 17 2 16 b2h 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 b3h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 the pwe value is compared against the value written to this location to enable pw1 access. at power-on, the pwe value is set to all ones. thus, writing these bytes to all ones grants pw1 access on power-on without writing the password entry. all reads of this register are 00h. factory default ffff ffffh read access n/a write access pw2 memory type nonvolatile (see) b4h 2 31 2 30 2 29 2 28 2 27 2 26 2 25 2 24 b5h 2 23 2 22 2 21 2 20 2 19 2 18 2 17 2 16 b6h 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 b7h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 the pwe value is compared against the value written to this location to enable pw2 access. at power-on, the pwe value is set to all ones. thus, writing these bytes to all ones grants pw2 access on power-on without writing the password entry. all reads of this register are 00h. table 02h, register b4h?7h: pw2
ds1873 sfp+ controller with analog ldd interface ______________________________________________________________________________________ 67 table 02h, register b8h: los ranging factory default 00h read access pw2 or (pw1 and rwtbl2) or (pw1 and rtbl2) write access pw2 or (pw1 and rwtbl2) memory type nonvolatile (see) b8h reserved hlos 2 hlos 1 hlos 0 reserved llos 2 llos 1 llos 0 bit 7 bit 0 this register controls the full-scale range of the quick-trip monitoring for the differential inputs of mon3. bit 7 reserved (default = 0) bits 6:4 hlos[2:0]: hlos full-scale ranging. 3-bit value to select the fs comparison voltage for high los found on mon3. default is 000b and creates an fs of 1.25v. hlos[2:0] % of 1.25v fs voltage 000b 100.00 1.250 001b 80.00 1.000 010b 66.67 0.833 011b 50.00 0.625 100b 40.00 0.500 101b 33.33 0.417 110b 28.57 0.357 111b 25.00 0.313 bit 3 reserved (default = 0) bits 2:0 llos[2:0]: llos full-scale ranging. 3-bit value to select the fs comparison voltage for low los found on mon3. default is 000b and creates an fs of 1.25v. llos[2:0] % of 1.25v fs voltage 000b 100.00 1.250 001b 80.00 1.000 010b 66.67 0.833 011b 50.00 0.625 100b 40.00 0.500 101b 33.33 0.417 110b 28.57 0.357 111b 25.00 0.313
ds1873 sfp+ controller with analog ldd interface 68 ______________________________________________________________________________________ table 02h, register b9h: comp ranging factory default 00h read access pw2 or (pw1 and rwtbl2) or (pw1 and rtbl2) write access pw2 or (pw1 and rwtbl2) memory type nonvolatile (see) b9h reserved hbias 2 hbias 1 hbias 0 reserved apc 2 apc 1 apc 0 bit 7 bit 0 the upper nibble of this byte controls the full-scale range of the quick-trip monitoring for bias. the lower nibble of this byte controls the full-scale range for the quick-trip monitoring of the apc reference as well as the closed-loop monitoring of apc. bit 7 reserved (default = 0) bits 6:4 hbias[2:0]: hbias full-scale ranging. 3-bit value to select the fs comparison voltage for bias found on mon1. default is 000b and creates an fs of 1.25v. hbias[2:0] % of 1.25v fs voltage 000b 100.00 1.250 001b 80.00 1.000 010b 66.67 0.833 011b 50.00 0.625 100b 40.00 0.500 101b 33.33 0.417 110b 28.57 0.357 111b 25.00 0.313 bit 3 reserved (default = 0) bits 2:0 apc[2:0]: apc full-scale ranging. 3-bit value to select the fs comparison voltage for mon2 with the apc. default is 000b and creates an fs of 2.5v. apc[2:0] % of 2.50v fs voltage 000b 100.00 2.500 001b 80.00 2.000 010b 66.67 1.667 011b 50.00 1.250 100b 40.00 1.000 101b 33.33 0.833 110b 28.57 0.714 111b 25.00 0.625
ds1873 sfp+ controller with analog ldd interface ______________________________________________________________________________________ 69 table 02h, register bah: ibiasmax factory default 00h read access pw2 or (pw1 and rwtbl2) or (pw1 and rtbl2) write access pw2 or (pw1 and rwtbl2) memory type nonvolatile (see) bah 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 bit 7 bit 0 this value defines the maximum dac value allowed for the upper 8 bits of bias output during apc closed-loop operations. during the intial step and binary search, this value does not cause an alarm, but does still clamp the bias dac value. after the startup sequence (or normal apc operations), if the apc loop tries to create a bias value greater than this setting, it is clamped and creates a max bias alarm. factory default 00h read access pw2 or (pw1 and rwtbl2) or (pw1 and rtbl2) write access pw2 or (pw1 and rwtbl2) memory type nonvolatile (see) bbh 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 bit 7 bit 0 the initial step value used at power-on or after a txd pulse to control the bias dac. at startup, this value plus 2 0 = 1 is continuously added to the bias dac value until the apc feedback (mon2) is greater t han its threshold. at that time, a binary search is used to complete the startup of the apc closed loop. if the resulting math operation is greater than ibiasmax (table 02h, register bah), the result is not loaded into the bias dac, but the binary search is begun to complete the initial search for apc. during startup, the bias dac steps causing a higher bias value than ibiasmax do not create the bias max alarm. the bias max alarm detection is enabled at the end of the binary search. table 02h, register bbh: istep
ds1873 sfp+ controller with analog ldd interface 70 ______________________________________________________________________________________ table 02h, register bdh: ltxp factory default 00h read access pw2 or (pw1 and rwtbl2) or (pw1 and rtbl2) write access pw2 or (pw1 and rwtbl2) memory type nonvolatile (see) bdh 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 fast-comparison dac threshold adjust for low txp. this value is subtracted from the apc dac value recalled from table 06h. if the difference is less than 0x00, 0x00 is used. comparisons less than v ltxp , compared against v mon2 , create a txp lo alarm. the same ranging applied to the apc dac should be used here. v ltxp = full scale 255 apc dac ltxp () factory default 00h read access pw2 or (pw1 and rwtbl2) or (pw1 and rtbl2) write access pw2 or (pw1 and rwtbl2) memory type nonvolatile (see) bch 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 fast-comparison dac threshold adjust for high txp. this value is added to the apc dac value recalled from table 06h. if the sum is greater than 0xff, 0xff is used. comparisons greater than v htxp , compared against v mon2 , create a txp hi alarm. the same ranging applied to the apc dac should be used here. v htxp = full scale 255 htxp + apc dac () table 02h, register bch: htxp
ds1873 sfp+ controller with analog ldd interface ______________________________________________________________________________________ 71 factory default 00h read access pw2 or (pw1 and rwtbl2) or (pw1 and rtbl2) write access pw2 or (pw1 and rwtbl2) memory type nonvolatile (see) beh 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 fast-comparison dac threshold adjust for high los. the combination of hlos and llos creates a hysteresis comparator. as rssi falls below the llos threshold, the los lo alarm bit is set to 1. the los alarm remains set until the rssi input is found above the hlos threshold setting, which clears the los lo alarm bit and sets the los hi alarm bit. at power-on, both los lo and los hi alarm bits are 0 and the hysteresis comparator uses the llos threshold setting. factory default 00h read access pw2 or (pw1 and rwtbl2) or (pw1 and rtbl2) write access pw2 or (pw1 and rwtbl2) memory type nonvolatile (see) bfh 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 fast-comparison dac threshold adjust for low los. see hlos (table 02h, register beh) for functi onal description. table 02h, register beh: hlos table 02h, register bfh: llos
ds1873 sfp+ controller with analog ldd interface 72 ______________________________________________________________________________________ table 02h, register c0h: pw_ena factory default 10h read access pw2 or (pw1 and rwtbl2) or (pw1 and rtbl2) write access pw2 or (pw1 and rwtbl2) memory type nonvolatile (see) c0h rwtbl78 rwtbl1c rwtbl2 rwtbl1a rwtbl1b wlower wauxa wauxb bit 7 bit 0 bit 7 rwtbl78: tables 07hC08h 0 = (default) read and write access for pw2 only. 1 = read and write access for both pw1 and pw2. bit 6 rwtbl1c: table 01h or 05h bytes f8hCffh. table address is dependent on mask bit (table 02h, register 89h). 0 = (default) read and write access for pw2 only. 1 = read and write access for both pw1 and pw2. bit 5 rwtbl2: tables 02h. writing a nonvolatile value to this bit requires pw2 access. 0 = (default) read and write access for pw2 only. 1 = read and write access for both pw1 and pw2. bit 4 rwtbl1a: table 01h, registers 80hCbfh 0 = read and write access for pw2 only. 1 = (default) read and write access for both pw1 and pw2. bit 3 rwtbl1b: table 01h, registers c0hCf7h 0 = (default) read and write access for pw2 only. 1 = read and write access for both pw1 and pw2. bit 2 wlower: bytes 00hC5fh in main memory. all users can read this area. 0 = (default) write access for pw2 only. 1 = write access for both pw1 and pw2. bit 1 wauxa: auxiliary memory, registers 00hC7fh. all users can read this area. 0 = (default) write access for pw2 only. 1 = write access for both pw1 and pw2. bit 0 wauxb: auxiliary memory, registers 80hCffh. all users can read this area. 0 = (default) write access for pw2 only. 1 = write access for both pw1 and pw2.
ds1873 sfp+ controller with analog ldd interface ______________________________________________________________________________________ 73 table 02h, register c1h: pw_enb factory default 03h read access pw2 or (pw1 and rwtbl2) or (pw1 and rtbl2) write access pw2 or (pw1 and rwtbl2) memory type nonvolatile (see) c1h rwtbl46 rtbl1c rtbl2 rtbl1a rtbl1b wpw1 wauxau wauxbu bit 7 bit 0 bit 7 rwtbl46: tables 04h and 06h 0 = (default) read and write access for pw2 only. 1 = read and write access for pw1. bit 6 rtbl1c: table 01h or table 05h, registers f8hCffh. table address is dependent on mask bit (table 02h, register 89h). 0 = (default) read access for pw2 only. 1 = read access for pw1. bit 5 rtbl2: table 02h 0 = (default) read access for pw2 only. 1 = read access for pw1. bit 4 rtbl1a: table 01h, registers 80hCbfh 0 = (default) read access for pw2 only. 1 = read access for pw1. bit 3 rtbl1b: table 01h, registers c0hCf7h 0 = (default) read access for pw2 only. 1 = read access for pw1. bit 2 wpw1: register pw1 (table 02h, registers b0hCb3h). for security purposes these registers are not readable. 0 = (default) write access for pw2 only. 1 = write access for pw1. bit 1 wauxau: auxiliary memory, registers 00hC7fh. all users can read this area. 0 = write access for pw2 only. 1 = (default) write access for user, pw1 and pw2. bit 0 wauxbu: auxiliary memory, registers 80hCffh. all users can read this area. 0 = write access for pw2 only. 1 = (default) write access for user, pw1 and pw2. table 02h, register c2h?5h: reserved factory default 00h read access pw2 or (pw1 and rwtbl2) or (pw1 and rtbl2) write access pw2 or (pw1 and rwtbl2) memory type nonvolatile (see) these registers are reserved.
ds1873 sfp+ controller with analog ldd interface 74 ______________________________________________________________________________________ table 02h, register c6h: polarity factory default 0ch read access pw2 or (pw1 and rwtbl2) or (pw1 and rtbl2) write access pw2 or (pw1 and rwtbl2) memory type nonvolatile (see) c6h reserved reserved reserved reserved modp biasp dac1p dac2p bit 7 bit 0 bits 7:4 reserved bit 3 modp: mod dac polarity. the mod dac (table 02h, registers 82hC83h) range is 000hC3ffh. a setting of 000h creates a pulse density of zero and 3ffh creates a pulse density of 1023/1024. this polarity bit allows the user to use gnd or v refin as the reference. the power-on of mod dac is 000h, thus an application that needs v refin to be in off state should use the inverted polarity. 0 = normal polarity. a setting of 000h results in a pulse-density output of zero held at gnd and a setting of 3ffh results in a pulsed-density output of 1023/1024 held mostly at v refin . 1 = inverted polarity. a setting of 000h results in a pulse-density output of zero held at v refin and a setting of 3ffh results in a pulsed-density output of 1023/1024 held mostly at gnd. bit 2 biasp: bias dac polarity. the bias dac (table 02h, registers cbhCcch) range is 000hC3ffh. a setting of 000h creates a pulse density of zero and 3ffh creates a pulse density of 1023/1024. this polarity bit allows the user to use gnd or v refin as the reference. the power-on of bias dac is 000h, thus an application that needs v refin to be the off state should use the inverted polarity. 0 = normal polarity. a setting of 000h results in a pulse-density output of zero held at gnd and a setting of 3ffh results in a pulsed-density output of 1023/1024 held mostly at v refin . 1 = inverted polarity. a setting of 000h results in a pulse-density output of zero held at v refin and a setting of 3ffh results in a pulsed-density output of 1023/1024 held mostly at gnd. bit 1 dac1p: dac1 value polarity. the dac1 value (table 02h, registers 84hC85h) range is 000hC 3ffh. a setting of 000h creates a pulse density of zero and 3ffh creates a pulse density of 1023/1024. this polarity bit allows the user to use gnd or v refin as the reference. the power-on of dac1 value is 000h, thus an application that needs v refin to be the off state should use the inverted polarity. 0 = normal polarity. a setting of 000h results in a pulse-density output of zero held at gnd and a setting of 3ffh results in a pulsed-density output of 1023/1024 held mostly at v refin . 1 = inverted polarity. a setting of 000h results in a pulse-density output of zero held at v refin and a setting of 3ffh results in a pulsed-density output of 1023/1024 held mostly at gnd. bit 0 dac2p: dac2 value polarity. the dac2 value (table 02h, registers 86hC87h) range is 000hC 3ffh. a setting of 000h creates a pulse-density of zero and 3ffh creates a pulse density of 1023/1024. this polarity bit allows the user to use gnd or v refin as the reference. the power-on of dac2 value is 000h, thus an application that needs v refin to be the off state should use the inverted polarity. 0 = normal polarity. a setting of 000h results in a pulse-density output of zero held at gnd and a setting of 3ffh results in a pulsed-density output of 1023/1024 held mostly at v refin . 1 = inverted polarity. a setting of 000h results in a pulse-density output of zero held at v refin and a setting of 3ffh results in a pulsed-density output of 1023/1024 held mostly at gnd.
ds1873 sfp+ controller with analog ldd interface ______________________________________________________________________________________ 75 table 02h, register c7h: tblselpon factory default 00h read access pw2 or (pw1 and rwtbl2) or (pw1 and rtbl2) write access pw2 or (pw1 and rwtbl2) memory type nonvolatile (see) c7h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 chooses the initial value for the table-select byte (lower memory, register 7fh) at power-on. factory default 0000h read access pw2 or (pw1 and rwtbl2) or (pw1 and rtbl2) write access (pw2 and bias en = 0) or (pw1 and rwtbl2 and bias en = 0) memory type volatile c8h 0 0 0 0 0 0 0 2 8 c9h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 when bias en (table 02h, register 80h) is written to 0, writes to these bytes control the bias dac. factory default 00h read access pw2 or (pw1 and rwtbl2) or (pw1 and rtbl2) write access (pw2 and bias en = 0) or (pw1 and rwtbl2 and bias en = 0) memory type volatile cah reserved reserved reserved reserved reserved reserved reserved man_clk bit 7 bit 0 when bias en (table 02h, register 80h) is written to 0, man_clk controls the updates of the man bias value to the bias dac. the values of man bias must be written with a separate write command. setting man_clk to a 1 clocks the man bias value to the bias dac. 1) write the man bias value with a write command. 2) set the man_clk bit to a 1 with a separate write command. 3) clear the man_clk bit to a 0 with a separate write command. table 02h, register c8h?9h: man bias table 02h, register cah: man_cntl
ds1873 sfp+ controller with analog ldd interface 76 ______________________________________________________________________________________ table 02h, register cbh?ch: bias dac factory default 0000h read access pw2 or (pw1 and rwtbl2) or (pw1 and rtbl2) write access n/a memory type volatile cbh reserved reserved reserved reserved reserved reserved 2 9 2 8 cch 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 the digital value used for bias and resolved from the apc. this register is updated after each decision of the apc loop. factory default 00h read access pw2 or (pw1 and rwtbl2) or (pw1 and rtbl2) write access n/a memory type n/a this register is reserved. factory default 73h read access pw2 or (pw1 and rwtbl2) or (pw1 and rtbl2) write access n/a memory type rom ceh 0 1 1 1 0 0 1 1 bit 7 bit 0 hardwired connections to show the device id. table 02h, register cdh: reserved table 02h, register ceh: device id
ds1873 sfp+ controller with analog ldd interface ______________________________________________________________________________________ 77 table 02h, register cfh: device ver factory default device version read access pw2 or (pw1 and rwtbl2) or (pw1 and rtbl2) write access n/a memory type rom cfh device version bit 7 bit 0 hardwired connections to show the device version. factory default 00h read access pw2 or (pw1 and rwtbl2) or (pw1 and rtbl2) write access (pw2 and apc en = 0) or (pw1 and rwtbl2 and apc en = 0) memory type volatile d0h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 the digital value used for apc reference and recalled from table 06h at the adjusted memory address found in tindex. this register is updated at the end of the temperature conversion. table 02h, register d0h: apc dac
ds1873 sfp+ controller with analog ldd interface 78 ______________________________________________________________________________________ table 02h, register d2h?7h: reserved factory default 00h read access pw2 or (pw1 and rwtbl2) or (pw1 and rtbl2) write access (pw2 and apc en = 0) or (pw1 and rwtbl2 and apc en = 0) memory type volatile d1h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 the digital value used for hbias reference and recalled from table 06h at the adjusted memory address found in tindex. this register is updated at the end of the temperature conversion. factory default 00h read access pw2 or (pw1 and rwtbl2) or (pw1 and rtbl2) write access n/a memory type n/a these registers are reserved. factory default 00h read access n/a write access n/a memory type none these registers do not exist. table 02h, register d1h: hbias dac table 02h, register d8h?fh: empty
ds1873 sfp+ controller with analog ldd interface ______________________________________________________________________________________ 79 table 04h, register f8h?fh: mod offset lut factory default 00h read access pw2 or (pw1 and rwtbl46) or (pw1 and rtbl46) write access pw2 or (pw1 and rwtbl46) memory type nonvolatile (ee) f8hCffh 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 bit 7 bit 0 the digital value for the temperature offset of the mod dac output. f8h less than or equal to -8c f9h greater than -8c up to +8c fah greater than +8c up to +24c fbh greater than +24c up to +40c fch greater than +40c up to +56c fdh greater than +56c up to +72c feh greater than +72c up to +88c ffh greater than +88c the mod dac is a 10-bit register. the modulation lut is an 8-bit lut. the mod offset lut times 4 plus the modulation lut makes use of the entire 10-bit range. factory default 00h read access pw2 or (pw1 and rwtbl46) or (pw1 and rtbl46) write access pw2 or (pw1 and rwtbl46) memory type nonvolatile (ee) 80hCc7h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 the digital value for the modulation dac output. the modulation lut is a set of registers assigned to hold the temperature profile for the mod dac. the values in this table determine the set point for the modulation voltage. the temperature measurement is used to index the lut (tindex, table 02h, register 81h) in 2c increments from -40c to +102c, starting at 80h in table 04h. register 80h defines the -40c to -38c mod output, register 81h defines the -38c to -36c mod output, and so on. values recalled from this eeprom memory table are written into the mod dac (table 02h, register 82hC83h) location that holds the value until the next temperature conversion. the ds1873 can be placed into a manual mode (mod en bit, table 02h, register 80h), where the mod dac is directly controlled for calibration. if the temperature compensation functionality is not required, then program the entire table 04h to the desired modulation setting. table 04h register description table 04h, register 80h?7h: modulation lut
ds1873 sfp+ controller with analog ldd interface 80 ______________________________________________________________________________________ table 06h register descriptions table 06h, register 80h?3h: apc lut factory default 00h read access pw2 or (pw1 and rwtbl46) or (pw1 and rtbl46) write access pw2 or (pw1 and rwtbl46) memory type nonvolatile (ee) 80hCa3h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 the apc lut is a set of registers assigned to hold the temperature profile for the apc reference dac. the values in this table combined with the apc bits in the comp ranging register (table 02h, register b9h) determine the set point for the apc loop. the temperature measurement is used to index the lut (tindex, table 02h, register 81h) in 4c increments from -40c to +100c, starting at register 80h. register 80h defines the -40c to -36c apc reference value, register 81h defines the -36c to -32c apc reference value, and so on. values recalled from this eeprom memory table are written into the apc dac (table 02h, register d0h) location that holds the value until the next temperature conversion. the ds1873 can be placed into a manual mode (apc en bit, table 02h, register 80h), where apc dac can be directly controlled for calibration. if te temperature compensation is not required by the application, program the entire lut to the desired apc set point. factory default 00h read access pw2 or (pw1 and rwtbl46) or (pw1 and rtbl46) write access pw2 or (pw1 and rwtbl46) memory type nonvolatile (ee) these registers are reserved. table 06h, register a4h?7h: reserved
ds1873 sfp+ controller with analog ldd interface ______________________________________________________________________________________ 81 factory default 00h read access pw2 or (pw1 and rwtbl46) or (pw1 and rtbl46) write access pw2 or (pw1 and rwtbl46) memory type nonvolatile (ee) f8hCffh 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 high bias alarm threshold (hbath) is a digital clamp used to ensure that the dac setting for bias currents does not exceed a set value. the table below shows the range of temp for each bytes location. the table shows a rising temperature; for a falling temperature there is 1c of hysteresis. f8h less than or equal to -8c f9h greater than -8c up to +8c fah greater than +8c up to +24c fbh greater than +24c up to +40c fch greater than +40c up to +56c fdh greater than +56c up to +72c feh greater than +72c up to +88c ffh greater than +88c table 06h, register f8h?fh: hbias lut table 07h register descriptions table 07h, register 80h?7h: dac1 lut factory default 00h read access pw2 or (pw1 and rwtbl78) or (pw1 and rtbl78) write access pw2 or (pw1 and rwtbl78) memory type nonvolatile (ee) 80hCc7h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 the dac1 lut is a set of registers assigned to hold the pwm profile for dac1. the values in this table determine the set point for dac1. the temperature measurement is used to index the lut (tindex, table 02h, register 81h) in 2c increments from -40c to +102c, starting at register 80h in table 07h. register 80h defines the -40c to -38c dac1 value, register 81h defines -38c to -36c dac1 value, and so on. values recalled from this eeprom memory table are written into the dac1 value (table 02h, registers 84hC85h) location, which holds the value until the next temperature conversion. the part can be placed into a manual mode (dac1 en bit, table 02h, register 80h), where dac1 can be directly controlled for calibration. if temperature compensation is not required by the application, program the entire lut to the desired dac1 set point.
ds1873 sfp+ controller with analog ldd interface 82 ______________________________________________________________________________________ factory default 00h read access pw2 or (pw1 and rwtbl78) or (pw1 and rtbl78) write access pw2 or (pw1 and rwtbl78) memory type nonvolatile (ee) f8hCffh 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 bit 7 bit 0 the digital value for the temperature offset of the dac1 output. f8h less than or equal to -8c f9h greater than -8c up to +8c fah greater than +8c up to +24c fbh greater than +24c up to +40c fch greater than +40c up to +56c fdh greater than +56c up to +72c feh greater than +72c up to +88c ffh greater than +88c the dac1 value is a 10-bit register. the dac1 lut is an 8-bit lut. the dac1 offset lut times 4 plus the dac1 lut makes use of the entire 10-bit range. table 07h, register f8h?fh: dac1 offset lut factory default 00h read access n/a write access n/a memory type none these registers do not exist. table 07h, register c8h?7h: empty
ds1873 sfp+ controller with analog ldd interface ______________________________________________________________________________________ 83 table 08h register descriptions table 08h, register 80h?3h: dac2 lut factory default 00h read access pw2 or (pw1 and rwtbl78) or (pw1 and rtbl78) write access pw2 or (pw1 and rwtbl78) memory type nonvolatile (ee) 80hCa3h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 the dac2 lut is set of registers assigned to hold the pwm profile for dac2. the values in this table determine the set point for dac2. the temperature measurement is used to index the lut (tindex, table 02h, register 81h) in 4c increments from -40c to +100c, starting at register 80h. register 80h defines the -40c to -36c dac2 value, register 81h defines -36c to -32c dac2 value, and so on. values recalled from this eeprom memory table are written into the dac2 value (table 02h, registers 86hC87h) location that holds the value until the next temperature conversion. the ds1873 can be placed into a manual mode (dac2 en bit, table 02h, register 80h), where dac2 can be directly controlled for calibration. if temperature compensation is not required by the application, program the entire lut to the desired dac2 set point. factory default 00h read access pw2 or (pw1 and rwtbl78) or (pw1 and rtbl78) write access pw2 or (pw1 and rwtbl78) memory type nonvolatile (ee) these registers are reserved. table 08h, register a4h?7h: reserved
ds1873 sfp+ controller with analog ldd interface 84 ______________________________________________________________________________________ factory default 00h read access all write access pw2 or (pw1 and wauxa) or wauxau memory type nonvolatile (ee) 00hC7fh 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 accessible with the slave address a0h. auxiliary memory a0h register descriptions auxiliary memory a0h, register 00h?fh: eeprom factory default 00h read access pw2 or (pw1 and rwtbl78) or (pw1 and rtbl78) write access pw2 or (pw1 and rwtbl78) memory type nonvolatile (ee) f8hCffh 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 bit 7 bit 0 the digital value for the temperature offset of the dac2 output. f8h less than or equal to -8c f9h greater than -8c up to +8c fah greater than +8c up to +24c fbh greater than +24c up to +40c fch greater than +40c up to +56c fdh greater than +56c up to +72c feh greater than +72c up to +88c ffh greater than +88c the dac2 value is a 10-bit register. the dac2 lut is an 8-bit lut. the dac2 offset lut times 4 plus the dac2 lut makes use of the entire 10-bit range. table 08h, register f8h?fh: dac2 offset lut
ds1873 sfp+ controller with analog ldd interface ______________________________________________________________________________________ 85 applications information power-supply decoupling to achieve best results, it is recommended that the power supply is decoupled with a 0.01? or a 0.1? capacitor. use high-quality, ceramic, surface-mount capacitors, and mount the capacitors as close as possible to the v cc and gnd pins to minimize lead inductance. sda and scl pullup resistors sda is an open-collector output on the ds1873 that requires a pullup resistor to realize high logic levels. a master using either an open-collector output with a pullup resistor or a push-pull output driver can be uti- lized for scl. pullup resistor values should be chosen to ensure that the rise and fall times listed in the i 2 c ac electrical characteristics table are within specification. package type package code document no. 28 tqfn-ep t2855+6 21-0140 factory default 00h read access all write access pw2 or (pw1 and rwauxb) or rwauxbu memory type nonvolatile (ee) 80hCffh 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 accessible with the slave address a0h. auxiliary memory a0h, register 80h?fh: eeprom package information for the latest package outline information and land patterns, go to www.maxim-ic.com/packages . note that a ?? ?? or ??in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status.
ds1873 sfp+ controller with analog ldd interface maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 86 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2009 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 0 9/09 initial release. changed the default state for the txdio bit in table 02h, register 8bh: cnfgc. 60 1 11/09 corrected the factory default value for table 02h, register c6h: polarity from 00h to 0ch. 74

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